Hot Reset; Figure 2.5 Fundamental Reset With Serial Eeprom Initialization - Renesas IDT 89HPES4T4 User Manual

IDT Clocking, Reset, and Initialization
Notes
PES4T4 User Manual
Serial EEPROM initialization may cause writes to register fields that initiate side effects such as link
retraining. These side effects are initiated at the point at which the write occurs. Therefore, serial EEPROM
initialization should be structured in a manner so as to ensure proper configuration prior to initiation of these
side effects.
A warm reset initiated by the writing of a one to the Fundamental Reset (FRST) bit in the Switch Control
(SWCTL) register always results in the PES4T4 returning a completion to the requester before the warm
reset process begins.
The PES4T4 provides a reset output signal for each downstream port implemented as a GPIO alternate
function. When a fundamental reset occurs, all of the GPIO pins default to GPIO inputs. Therefore, the
downstream port resets are tri-stated. A system designer should use a pull-down on these signals if they
are used as reset outputs.
The operation of a fundamental reset with serial EEPROM initialization (i.e., SWMODE[2:0] = 0x1) is
illustrated in Figure 2.5.
REFCLK
Tpvperl
Vdd
PERSTN
RSTHALT
SerDes
PLL Reset and Lock
Master SMBus
Notes:
1) Reference Clock (REFCLK) not shown to scale.
2) The PES4T4 requires a minimum time for Tperst-clk of 1µs. The PES4T4 requires a minimum time for Tpvperl of 1ms.
3) In a system, the values of Tpvperl and Tperst-clk depend on the mechanical form factor in which the PES4T4 is used. For example,
the PCIe Card Electromechanical Specification, Revision 2.0, specifies minimum values of Tperst-clk=100µs and Tpvperl=100ms.

Figure 2.5 Fundamental Reset with Serial EEPROM initialization

Hot Reset

A hot reset may be initiated by any of the following conditions:
– Reception of TS1 ordered-sets on the upstream port indicating a hot reset.
– Data link layer of the upstream port transitions to the DL_Down state.
– Writing a one to the Hot Reset (HRST) bit in the Switch Control (SWCTL) register.
The initiation of a hot reset due to the data link layer of the upstream port transitioning to the DL_Down
state may be disabled by setting the Disable Link Down Hot Reset (DLDHRST) bit in the Switch Control
(SWCTL) register. Other hot reset conditions are unaffected by this bit.
20ms max.
11μs
CDR Reset & Lock
1.01 ms max.
Idle Serial EEPROM Initialization
2 - 6
Clock Operation
Link Training Ready for Normal Operation
Ready
February 1, 2011