Table of Contents
Advertisement
Notes
PES4T4 User Manual
®
Port Interrupts
The upstream port (Port 0) generates legacy interrupts and MSIs to report internal switch errors such as
parity errors and errors in reading configuration registers. Downstream ports support generation of legacy
interrupts and MSIs. The following are sources of downstream port interrupts and MSIs.
– Downstream port's hot-plug controller
– Link bandwidth notification capability (i.e., assertion of the LBWSTS or LABWSTS bits in the
PCIELSTS register when interrupt notification is enabled for these bits)
When a downstream port is configured to generate INTx messages, only INTA is used. When an
unmasked interrupt condition occurs, then an MSI or interrupt message is generated by the corresponding
port as described in Table 3.1. The removal of the interrupt condition occurs when unmasked status bit(s)
causing the interrupt are masked or cleared.
The PES4T4 assumes that all downstream port generated MSIs are targeted to the root and routes
these transactions to the upstream port. Configuring the address contained in a downstream port's
MSIADDR and MSIADDRU registers to an address that does not route to the upstream port and generating
an MSI produces undefined results.
EN bit in
Unmasked
MSICAP
Interrupt
Register
Asserted
1
0
0
Negated
1
0
0
Since memory error reporting via interrupts is an optional capability, the MSI capability structure associ-
ated with the upstream port is not by default part of the PCI capability structure link list located in the
upstream port's configuration space. This capability may be added to the capability structure linked list by
using the serial EEPROM, SMBus or the Root to unlock registers and setting the Next Pointer (NXTPTR)
field in the PCI Power Management Capabilities (PMCAP) register to 0xD0.
Legacy Interrupt Emulation
The PES4T4 supports legacy PCI INTx emulation. Rather than use sideband INTx signals, PCIe defines
two messages that indicate the assertion and negation of an interrupt signal. An Assert_INTx message is
used to signal the assertion of an interrupt signal and an Deassert_INTx message is used to signal its nega-
tion.
Theory of Operation
INTXD bit
in PCICMD
Register
X
MSI message generated
0
Assert_INTA message request generated to switch
core
1
None
X
None
0
Deassert_INTA message request generated to
switch core
1
None
Table 3.1 Downstream Port Interrupts
3 - 1
Chapter 3
Action
February 1, 2011
Advertisement
Table of Contents
