Appendix D: Post Error Codes; Post Boot Behavior; Rom Init; Initial Post - ADIC Scalar 100 User Manual
Quantum scalar 100: user guide
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Also See for Scalar 100:
- User manual (346 pages) ,
- Quick start manual (2 pages) ,
- Release note (2 pages)
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Appendix D: POST Error
Codes
The Power-On-Self-Test (POST) is responsible for testing the integrity of the processor's
SDRAM. After testing SDRAM POST will attempt to transfer control to either the default
bootrom image or an alternate image. POST can also download binary images over the
service port and write them to flash memory. This enables POST to perform a minimal
amount of emergency recovery from FLASH errors.
POST Boot Behavior
ROM Init
P
-
OWER
ON
Figure D-1: ROM Init
After applying power the ERR LED will illuminate. At this time postInit code initial-
izes the processor's internal registers and subsystems, including the SDRAM controller.
The processor's internal RAM is used as a tiny-stack for this stage of POST. Control is
then passed to the IpostMain routine for the SDRAM memory.
Initial POST
PLD
S
P
I
AND
ERVICE
ORT
NITIALIZATION
Figure D-2: Initial POST
page 255
POST Error Codes
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