Renesas R5F56104WDBG Manuals

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Renesas R5F56104WDBG User Manual

Renesas R5F56104WDBG User Manual (1006 pages)

32-Bit MCU

Brand: Renesas | Category: Microcontrollers | Size: 12 MB

Table of Contents

Table of Contents
7
Contents
7
Overview
28
Features
28
Applications
28
Outline of Specifications
29
List of Products
32
Block Diagram
34
Pin Assignments
35
Pin Functions
49
Cpu
54
Features
54
Register Set of the CPU
55
General-Purpose Registers (R0 to R15)
56
Control Registers
56
Interrupt Stack Pointer (Isp)/User Stack Pointer (USP)
57
Interrupt Table Register (INTB)
57
Program Counter (PC)
57
Processor Status Word (PSW)
58
Backup PC (BPC)
60
Backup PSW (BPSW)
60
Fast Interrupt Vector Register (FINTV)
60
Floating-Point Status Word (FPSW)
61
Accumulator (ACC)
64
Processor Mode
65
Supervisor Mode
65
User Mode
65
Privileged Instruction
65
Switching between Processor Modes
65
Data Types
66
Integer
66
Floating-Point
66
Bitwise Operations
67
Strings
67
Endian
68
Switching the Endian
68
Access to I/O Registers
72
Notes on Access to I/O Registers
72
Data Arrangement
73
Data Arrangement in Registers
73
Data Arrangement in Memory
73
Notes on Arrangement of Instruction Code
73
Vector Table
74
Fixed Vector Table
74
Relocatable Vector Table
75
Operation of Instructions
76
Data Prefetching by the RMPA Instruction and the String-Manipulation Instructions
76
Pipeline
77
Overview
77
Instructions and Pipeline Processing
79
Instructions Converted into Single Micro-Operation and Pipeline Processing
79
Instructions Converted into Multiple Micro-Operations and Pipeline Processing
81
Pipeline Basic Operation
84
Calculation of the Instruction Processing Time
86
Numbers of Cycles for Response to Interrupts
87
Operating Modes
88
Operating Mode Types and Selection
88
Register Descriptions
89
Mode Monitor Register (MDMONR)
89
Mode Status Register (MDSR)
90
System Control Register 0 (SYSCR0)
91
System Control Register 1 (SYSCR1)
93
Details of Operating Modes
94
Single-Chip Mode
94
On-Chip ROM Enabled Extended Mode
94
On-Chip ROM Disabled Extended Mode
94
Boot Mode
94
User Boot Mode
94
Transitions of Operating Modes
95
Operating Mode Transitions According to Mode Pin Setting
95
Operating Mode Transitions According to Register Setting
96
Address Space
97
External Address Space
101
I/O Registers
102
I/O Register Addresses (Address Order)
104
I/O Register Bits
125
Resets
154
Overview
154
Register Descriptions
156
Reset Status Register (RSTSR)
156
Reset Control/Status Register (RSTCSR)
157
Operation
158
Pin Reset
158
Deep Software Standby Reset
158
Watchdog Timer Reset
158
Determining Reset Generation Source
159
Usage Notes
159
Notes on Design of Board
159
Clock Generation Circuit
160
Overview
160
Register Descriptions
161
System Clock Control Register (SCKCR)
162
Main Clock Oscillator
164
Connecting a Crystal Resonator
164
External Clock Input
165
PLL Circuit
165
Frequency Divider
165
Internal Clock
166
System Clock (ICLK)
166
Peripheral Module Clock (PCLK)
166
External Bus Clock (BCLK)
166
Usage Notes
167
Notes on the Clock Generation Circuit
167
Notes on Resonator
168
Notes on Board Design
168
Low Power Consumption
169
Overview
169
Register Descriptions
172
Standby Control Register (SBYCR)
174
Module Stop Control Register a (MSTPCRA)
176
Module Stop Control Register B (MSTPCRB)
178
Module Stop Control Register C (MSTPCRC)
179
Deep Standby Control Register (DPSBYCR)
181
Deep Standby Wait Control Register (DPSWCR)
182
Deep Standby Interrupt Enable Register (DPSIER)
183
Deep Standby Interrupt Flag Register (DPSIFR)
184
Deep Standby Interrupt Edge Register (DPSIEGR)
185
Reset Status Register (RSTSR)
186
Deep Standby Backup Register (Dpsbkry) (y = 0 to 31)
187
Multi-Clock Function
188
Module Stop Function
188
Low Power Consumption Modes
188
Sleep Mode
189
Transition to Sleep Mode
189
Canceling Sleep Mode
189
All-Module Clock Stop Mode
189
Transitions to All-Module Clock Stop Mode
190
Release from All-Module Clock Stop Mode
190
Software Standby Mode
192
Transition to Software Standby Mode
192
Canceling Software Standby Mode
192
Setting Oscillation Settling Time after Software Standby Mode Is Canceled
193
Example of Software Standby Mode Application
194
Deep Software Standby Mode
195
Transition to Deep Software Standby Mode
195
Canceling Deep Software Standby Mode
196
Pin States When Deep Software Standby Mode Is Canceled
196
Setting Oscillation Settling Time after Deep Software Standby Mode Is Canceled
197
Example of Deep Software Standby Mode Application
198
Flowchart to Use Deep Software Standby Mode
199
BCLK Output Control
201
Usage Notes
202
I/O Port States
202
Module Stop State of the DMAC and DTC
202
On-Chip Peripheral Module Interrupts
202
Write-Access to MSTPCRA, MSTPCRB, and MSTPCRC
202
Input Buffer Control by Dirqne Bit (N = 3 to 0)
202
Conflict between Transition to Deep Software Standby Mode and Interrupt
202
Timing of Wait Instructions
202
Exceptions
203
Types of Exceptions
203
Undefined Instruction Exception
204
Privileged Instruction Exception
204
Floating-Point Exceptions
204
Reset
204
Non-Maskable Interrupt
204
Interrupts
204
Unconditional Trap
204
Exception Handling Procedure
205
Acceptance of Exceptions
207
Timing of Acceptance and Saved PC Values
207
Vector and Site for Saving the Values in the PC and PSW
208
Hardware Processing for Accepting and Returning from Exceptions
209
Hardware Pre-Processing
210
Undefined Instruction Exception
210
Privileged Instruction Exception
210
Floating-Point Exceptions
210
Reset
210
Non-Maskable Interrupt
211
Interrupts
211
Unconditional Trap
211
Return from Exception Handling Routines
212
Order of Priority for Exceptions
212
Interrupt Control Unit (ICU)
213
Overview
213
Register Descriptions
215
Interrupt Request Register I (Iri) (I = Interrupt Vector Number)
223
Interrupt Request Destination Setting Register I (Iselri) (I = Interrupt Vector Number)
225
Interrupt Request Enable Register M (Ieri) (I = 02H to 1Fh)
226
Interrupt Priority Register I (Ipri) (I = 00H to 8Fh)
227
Fast Interrupt Register (FIR)
228
IRQ Detection Enable Register N (Irqern) (N = 0 to 15)
229
IRQ Control Register N (Irqcrn) (N = 0 to 15)
230
Non-Maskable Interrupt Enable Register (NMIER)
231
NMI Pin Interrupt Control Register (NMICR)
232
Non-Maskable Interrupt Status Register (NMISR)
233
Non-Maskable Interrupt Clear Register (NMICLR)
234
Software Standby Release IRQ Enable Register (SSIER)
235
Vector Table
236
Interrupt Vector Table
236
Fast Interrupt Vector Address
241
Non-Maskable Interrupt Vector Address
241
Operation
242
Enabling and Disabling Interrupts
242
Interrupt Status Flag
243
Interrupt Status Flag in Edge Detection
243
Interrupt Status Flag in Level Detection
244
Selecting Interrupt Request Destinations
246
Determining Priority
248
Fast Interrupt
248
External Interrupts
249
Non-Maskable Interrupt Operation
250
Returning from Low Power Consumption Modes
251
Returning from Sleep Mode and All-Module Clock Stop Mode
251
Returning from Software Standby Mode
252
Usage Notes
253
Notes When Writing to the Register of the Interrupt Control Unit
253
Notes on the WAIT Instruction When the NMI Pin Interrupt Is Used
253
Notes on Transferring DMAC/DTC Using Communication Function (SCI, RIIC)
253
Buses
256
Overview
256
Description of Buses
257
CPU Buses
257
Internal Main Buses
257
Internal Peripheral Buses
258
External Bus
258
Parallel Operation
260
Register Descriptions
261
Csi Control Register (Csicnt) (I = 0 to 7)
263
Csi Recovery Cycle Register (Csirec) (I = 0 to 7)
265
Csi Mode Register (Csimod) (I = 0 to 7)
267
Csi Wait Control Register 1 (Csiwcnt1) (I = 0 to 7)
269
Csi Wait Control Register 2 (Csiwcnt2) (I = 0 to 7)
273
Bus Error Source Clear Register (BERCLR)
277
Bus Error Monitoring Enable Register (BEREN)
277
Bus Error Interrupt Enable Register (BERIE)
278
Endian and Data Alignment
279
16-Bit Bus Space
279
8-Bit Bus Space
280
Operation
283
Timing of External Bus Access
283
Normal Access
285
Page Access
290
External Wait Function
293
Normal Access
293
Page Access
293
Insertion of Recovery Cycles
295
Write Buffer Function
296
Notes on Usage
297
Limitations at the Time of Normal and Page Access
297
Prohibition of Access that Spans Areas of Address Space
297
Restrictions in Relation to RMPA and String-Manipulation Instructions
297
Point for Caution Regarding Register Settings
297
Restriction on Instruction Code
298
Bus Error Monitoring Section
299
Types of Bus Error
299
Illegal Address Access
299
Time-Out
299
Operations When a Bus Error Occurs
299
Conditions Leading to Bus Errors
300
DMA Controller (DMAC)
301
Overview
301
Register Descriptions
303
DMA Mode Register (DMMOD)
305
DMA Control Register a (DMCRA)
307
DMA Control Register B (DMCRB)
310
DMA Control Register C (DMCRC)
311
DMA Control Register D (DMCRD)
312
DMA Control Register E (DMCRE)
313
DMA Current Transfer Source Address Register (DMCSA)
314
DMA Current Transfer Destination Address Register (DMCDA)
315
DMA Current Transfer Byte Count Register (DMCBC)
316
DMA Reload Transfer Source Address Register (DMRSA)
317
DMA Reload Transfer Destination Address Register (DMRDA)
317
DMA Reload Transfer Byte Count Register (DMRBC)
318
DMA Interrupt Control Register (DMICNT)
319
DMA Start Register (DMSCNT)
320
DMA Arbitration Status Register (DMASTS)
321
DMA Transfer End Detect Register (DMEDET)
322
Operation
323
Bus Mastership Release Timing
323
Transfer System
324
Activating the DMAC
326
Starting DMA Transfer
327
Ending DMA Transfer
327
Suspending, Restarting, and Canceling DMA Transfer
328
DMA Activation Source
329
Software Trigger
329
Interrupt Signals on External Pins and Peripheral Function Interrupts
329
Channel Arbitration
330
Reload Function
330
Rotate
331
Interrupts
331
Low-Power Consumption
332
Usage Notes
333
Register Settings
333
DMA Transfer to External Devices
333
Data Transfer Controller (DTC)
334
Overview
334
Register Descriptions
336
DTC Mode Register a (MRA)
337
DTC Mode Register B (MRB)
338
DTC Source Address Register (SAR)
339
DTC Destination Address Register (DAR)
339
DTC Transfer Count Register a (CRA)
340
DTC Transfer Count Register B (CRB)
341
DTC Control Register (DTCCR)
341
DTC Vector Base Register (DTCVBR)
342
DTC Address Mode Register (DTCADMOD)
343
DTC Module Start Register (DTCST)
343
Sources of Activation
344
Allocating Transfer Data and DTC Vector Table
344
Startup Source and Vector Address
346
Operation
349
Transfer Data Read Skip Function
352
Transfer Data Write-Back Skip Function
353
Normal Transfer Mode
354
Repeat Transfer Mode
355
Block Transfer Mode
357
Chain Transfer
358
Operation Timing
359
Execution Cycle of the DTC
361
DTC Bus Mastership Release Timing
361
DTC Setting Procedure
362
Examples of DTC Usage
363
Chain Transfer
364
Chain Transfer When Counter = 0
365
Interrupt Source
367
Allocating Transfer Data
368
Overview
369
Register Descriptions
375
Data Direction Register (DDR)
378
Data Register (DR)
379
Port Register (PORT)
380
Input Buffer Control Register (ICR)
381
Pull-Up Resistor Control Register (PCR)
382
Open Drain Control Register (ODR)
383
Port Function Control Register 1 (PFCR1)
384
Port Function Control Register 2 (PFCR2)
386
Port Function Control Register 3 (PFCR3)
387
Port Function Control Register 4 (PFCR4)
388
Port Function Control Register 5 (PFCR5)
389
Port Function Control Register 6 (PFCR6)
390
Port Function Control Register 7 (PFCR7)
393
Port Function Control Register 8 (PFCR8)
396
Port Function Control Register 9 (PFCR9)
397
Settings of Ports
398
Port 1 (P1)
400
Port 2 (P2)
402
Port 3 (P3)
405
Port 4 (P4)
408
Port 5 (P5)
410
Port 6 (P6)
412
Port 7 (P7)
415
Port 8 (P8)
417
Port 9 (P9)
419
Port a (PA)
421
Port B (PB)
425
Port C (PC)
428
Port D (PD)
431
Port F (PF)
432
Port G (PG)
434
Port H (PH)
436
Settings to Enable Output of the Signals
438
Treatment of Unused Pins
446
I/O Port Configuration
447
Usage Notes
451
Overview
452
Register Descriptions
460
Timer Control Register (TCR)
463
Timer Mode Register (TMDR)
467
Timer I/O Control Register (TIORH, TIORL, TIOR)
469
Timer Interrupt Enable Register (TIER)
479
Timer Status Register (TSR)
481
Timer Counter (TCNT)
482
Timer Start Register (TSTRA, TSTRB)
483
Timer Synchronous Register (TSYRA, TSYRB)
484
Operation
485
Synchronous Operation
490
Buffer Operation
492
Cascaded Operation
496
PWM Modes
498
Phase Counting Mode
503
Phase Counting Mode Application Example
508
Interrupt Sources
509
DTC Activation
512
Operation Timing
513
Interrupt Signal Timing
517
Usage Notes
519
Caution on Cycle Setting
520
Conflict between Tpum.tgry Write and Compare Match
521
Conflict between Tpum.tgry Read and Input Capture
522
Conflict between Buffer Register Write and Input Capture
523
Conflict between Tpum.tcnt Write and Overflow/Underflow
524
Overview
525
Register Descriptions
529
PPG Trigger Select Register (PTRSLR)
530
Next Data Enable Registers H and L (NDERH, NDERL)
531
Output Data Registers H and L (PODRH, PODRL)
535
Next Data Registers H and L (NDRH, NDRL)
537
PPG Output Control Register (PCR)
542
PPG Output Mode Register (PMR)
544
Operation
547
Output Timing
548
Sample Setup Procedure for Normal Pulse Output
549
Example of Normal Pulse Output (Example of Five-Phase Pulse Output)
551
Non-Overlapping Pulse Output
552
Sample Setup Procedure for Non-Overlapping Pulse Output
554
Example of Non-Overlapping Pulse Output (Example of Four-Phase Complementary Non-Overlapping Output)
556
Inverted Pulse Output
558
Pulse Output Triggered by Input Capture
559
Usage Note
560
Overview
561
Register Descriptions
565
Timer Counter (TCNT)
566
Time Constant Register B (TCORB)
567
Timer Control Register (TCR)
568
Timer Counter Control Register (TCCR)
569
Timer Control/Status Register (TCSR)
571
Operation
573
Reset Input
574
Operation Timing
575
Timing of Interrupt Flag Setting to 1 at Compare Match
576
Timing of Timer Output at Compare Match
577
Timing of the External Reset for TCNT
578
Timing of Overflow Interrupt Flag Setting to 1
579
Operation with Cascaded Connection
580
Interrupt Sources
581
Usage Notes
582
Conflict between TCNT Write and Increment
583
Conflict between TCORA or TCORB Write and Compare Match
584
Switching of Internal Clocks and TCNT Operation
585
Clock Source Setting with Cascaded Connection
586
Overview
587
Register Descriptions
588
Compare Match Timer Start Register 0 (CMSTR0)
589
Compare Match Timer Start Register 1 (CMSTR1)
590
Compare Match Timer Control Register (CMCR)
591
Compare Match Counter (CMCNT)
592
Operation
593
Interrupts
594
Usage Notes
595
Notes on Rewriting Compare Match Timer Control Register (CMCR)
596
Overview
597
Register Descriptions
599
Timer Control/Status Register (TCSR)
600
Reset Control/Status Register (RSTCSR)
601
Write Window a Register (WINA)
602
Operation
603
Interval Timer Mode
604
Usage Notes
605
Conflict between Timer Counter (TCNT) Write and Increment
606
Switching between Watchdog Timer Mode and Interval Timer Mode
607
Overview
608
Register Descriptions
612
Receive Shift Register (RSR)
614
Transmit Shift Register (TSR)
615
Serial Control Register (SCR)
619
Serial Status Register (SSR)
624
Smart Card Mode Register (SCMR)
630
Bit Rate Register (BRR)
632
Serial Extended Mode Register (SEMR)
639
Operation in Asynchronous Mode
641
Serial Data Transfer Format
642
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
643
Clock
644
SCI Initialization (Asynchronous Mode)
645
Serial Data Transmission (Asynchronous Mode)
646
Serial Data Reception (Asynchronous Mode)
648
Operation in Clock Synchronous Mode
652
SCI Initialization (Clock Synchronous Mode)
653
Serial Data Transmission (Clock Synchronous Mode)
654
Serial Data Reception (Clock Synchronous Mode)
656
Simultaneous Serial Data (Clock Synchronous Mode)
658
Operation in Smart Card Interface Mode
660
Data Format (Except in Block Transfer Mode)
661
Block Transfer Mode
662
Receive Data Sampling Timing and Reception Margin
663
Initialization of the SCI
665
Serial Data Transmission (Except in Block Transfer Mode)
666
Serial Data Reception (Except in Block Transfer Mode)
669
Clock Output Control
670
Interrupt Sources
672
Interrupts in Smart Card Interface Mode
673
Usage Notes
674
Restrictions on Clock Synchronous Transmission
675
External Clock Input in Clock Synchronous Mode
678
Overview
679
Register Descriptions
680
CRC Data Input Register (CRCDIR)
681
Operation
682
Usage Notes
685
Overview
686
Register Descriptions
690
Slave Address Register Ly (Sarly) (y = 0 to 2)
720
Slave Address Register Uy (Saruy) (y = 0 to 2)
721
Internal Counter for Timeout (TMOCNT)
726
Operation
727
Initial Settings
728
Master Transmitter Operation
729
Master Receiver Operation
733
Slave Transmitter Operation
738
Slave Receiver Operation
741
SCL Synchronization Circuit
744
Facility for Delaying SDA Output
745
Digital Noise-Filter Circuits
746
Address Match Detection
747
Detection of the General Call Address
749
Device-ID Address Detection
750
Host Address Detection
752
Function to Automatically Hold Scln Clock Low
753
NACK Reception Transfer Suspension Function
754
Function to Prevent Failure to Receive Data
755
Arbitration-Lost Detection Functions
757
Function to Detect Loss of Arbitration During NACK Transmission (NALE Bit)
759
Slave Arbitration Lost Detection (SALE Bit)
760
Start Condition/Restart Condition/Stop Condition Issuing Function
761
Issuing a Stop Condition
762
Bus Hanging
763
Extra SCL Clock Cycle Output Function
765
RIIC Reset and Internal Reset
766
Smbus Operation
767
Packet Error Code (PEC)
768
Smbus Host Notification Protocol/Notify ARP Master
769
Interrupt Request
770
Reset States
771
Usage Notes
772
Notes When Communication Is Restarted with the NACK Reception in Master Mode
773
Overview
774
Register Descriptions
781
A/D Data Register y (Addry) (y = a to D)
782
A/D Control/Status Register (ADCSR)
783
A/D Control Register (ADCR)
785
Addry Format Select Register (ADDPR)
787
Operation
788
Scan Mode
790
Single Scan Mode
792
Input Sampling and A/D Conversion Time
793
Activation by External Triggers
795
Activation by the Compare-Match/Input-Capture a to D Signals from TPU0
796
Activation by the Compare-Match/Input-Capture a Signals from TPU0 to TPU5
797
Activation on Compare-Match of TMR Units
798
Interrupt Source
799
Usage Notes
801
Permissible Impedance of Signal Sources
802
Ranges of Settings for Analog Power Supply and Other Pins
803
Point for Caution Regarding Countermeasures for Noise
804
Realizing High-Speed Conversion
805
Notes When Using Multiple Units of A/D Converter
806
Overview
808
Register Descriptions
810
D/A Control Register (DACR)
811
Dadry Format Select Register (DADPR)
813
Operation
814
Usage Notes
815
Overview
817
Overview
818
Register Descriptions
821
Flash Mode Register (FMODR)
822
Flash Access Status Register (FASTAT)
823
Flash Access Error Interrupt Enable Register (FAEINT)
825
FCU RAM Enable Register (FCURAME)
826
Flash Status Register 0 (FSTATR0)
827
Flash Status Register 1 (FSTATR1)
830
Flash Ready Interrupt Enable Register (FRDYIE)
831
Flash P/E Mode Entry Register (FENTRYR)
832
Flash Protection Register (FPROTR)
835
Flash Reset Register (FRESETR)
836
FCU Command Register (FCMDR)
837
FCU Processing Switching Register (FCPSR)
838
Flash P/E Status Register (FPESTAT)
839
Peripheral Clock Notification Register (PCKAR)
840
Flash Write Erase Protection Register (FWEPROR)
841
Configuration of Memory Mats for the ROM
842
Operating Modes Associated with the ROM
843
Programming and Erasing the ROM
846
ROM Read Modes
847
FCU Commands
848
Connections between FCU Modes and Commands
850
FCU Command Usage
851
Programming and Erasure Procedures
855
Error Processing
864
Suspension and Resumption
865
Suspending Operation
868
Suspension During Erasure (Suspension Priority Mode)
869
Suspension During Erasure (Erasure Priority Mode)
870
Protection
871
User Boot Mode
873
ID Code Protection
874
State Transitions in Boot Mode
876
Automatic Adjustment of the Bit Rate
878
Inquiry/Selection Host Command Wait State
879
ID Code Wait State
893
Programming/Erasure Host Command Wait State
894
ID Code Protection on Connection of the On-Chip Debugger
903
ROM Code Protection
904
Usage Notes
905
Overview
907
Register Descriptions
909
Flash Mode Register (FMODR)
910
Flash Access Status Register (FASTAT)
911
Flash Access Error Interrupt Enable Register (FAEINT)
913
Data Flash Read Enable Register (DFLRE)
915
Data Flash Programming/Erasure Enable Register (DFLWE)
916
Flash P/E Mode Entry Register (FENTRYR)
917
Data Flash Blank Check Control Register (DFLBCCNT)
919
Data Flash Blank Check Status Register (DFLBCSTAT)
920
Configuration of Memory Mat for the Data Flash Memory
921
Operating Modes Associated with the Data Flash
922
Programming and Erasing the Data Flash Memory
923
ROM P/E Modes
924
FCU Commands
925
Connections between FCU Modes and Commands
926
FCU Command Usage
927
Protection
931
Error Protection
932
Boot Mode
933
Programming/Erasing Host Commands
935
Usage Notes
936
Features
937
Register Descriptions
938
Instruction Register (JTIR)
939
IDCODE Register (JTID)
948
Operations
949
List of Commands
950
Usage Notes
952
Absolute Maximum Ratings
954
DC Characteristics
955
AC Characteristics
958
Control Signal Timing
962
Bus Timing
963
Timing of On-Chip Peripheral Modules
968
A/D Conversion Characteristics
976
ROM (Flash Memory for Code Storage) Characteristics
977
Data Flash (Flash Memory for Data Storage) Characteristics
978

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