Figure 438. Reception Using Dma; Figure 439. Hardware Flow Control Between 2 Lpuarts - ST STM32L4 5 Series Reference Manual

Low-power universal asynchronous receiver transmitter (LPUART)
Error flagging and interrupt generation in multibuffer communication
In multibuffer communication if any error occurs during the transaction the error flag is
asserted after the current byte. An interrupt is generated if the interrupt enable flag is set.
For framing error, overrun error and noise flag which are asserted with RXNE in single byte
reception, there is a separate error flag interrupt enable bit (EIE bit in the LPUART_CR3
register), which, if set, enables an interrupt after the current byte if any of these errors occur.
41.4.10 RS232 Hardware flow control and RS485 Driver Enable
using LPUART
It is possible to control the serial data flow between 2 devices by using the CTS input and
the RTS output. The
RS232 RTS and CTS flow control can be enabled independently by writing the RTSE and
CTSE bits respectively to 1 (in the LPUART_CR3 register).
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Figure 438. Reception using DMA

Figure 427 shows how to connect 2 devices in this mode:

Figure 439. Hardware flow control between 2 LPUARTs

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