ST STM32L4 5 Series Reference Manual page 1405

RM0351
Bits 31:4 Reserved, must be kept at reset value
Bit 3 RXFRQ: Receive data flush request
Bit 2 MMRQ: Mute mode request
Bit 1 SBKRQ: Send break request
Note: In the case the application needs to send the break character following all previously
Bit 0 Reserved, must be kept at reset value
41.7.6 Interrupt & status register (LPUART_ISR)
Address offset: 0x1C
Reset value: 0x00C0
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:23 Reserved, must be kept at reset value.
Bit 22 REACK: Receive enable acknowledge flag
Note: If the LPUART does not support the wakeup from Stop feature, this bit is reserved and
Bit 21 TEACK: Transmit enable acknowledge flag
Bit 20 WUF: Wakeup from Stop mode flag
This bit is set by hardware, when a wakeup event is detected. The event is defined by the
WUS bit field. It is cleared by software, writing a 1 to the WUCF in the LPUART_ICR register.
An interrupt is generated if WUFIE=1 in the LPUART_CR3 register.
Note: When UESM is cleared, WUF flag is also cleared.
Low-power universal asynchronous receiver transmitter (LPUART)
Writing 1 to this bit clears the RXNE flag.
This allows to discard the received data without reading it, and avoid an overrun condition.
Writing 1 to this bit puts the LPUART in mute mode and resets the RWU flag.
Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as
the transmit machine is available.
inserted data, including the ones not yet transmitted, the software should wait for the
TXE flag assertion before setting the SBKRQ bit.
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. CTS CTSIF
r r
This bit is set/reset by hardware, when the Receive Enable value is taken into account by
the LPUART.
It can be used to verify that the LPUART is ready for reception before entering Stop mode.
forced by hardware to '0'.
This bit is set/reset by hardware, when the Transmit Enable value is taken into account by
the LPUART.
It can be used when an idle frame request is generated by writing TE=0, followed by TE=1
in the LPUART_CR1 register, in order to respect the TE=0 minimum period.
The WUF interrupt is active only in Stop mode.
If the LPUART does not support the wakeup from Stop feature, this bit is reserved and
forced by hardware to '0'.
24 23 22
RE
Res. Res.
ACK
r
8 7 6
Res. TXE TC
r r
DocID024597 Rev 5
21 20 19 18
TE
WUF RWU SBKF
ACK
r r r
5 4 3 2
RXNE IDLE ORE NF
r r r
17 16
CMF BUSY
r r r
1 0
FE PE
r r r
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