ST STM32L4 5 Series Reference Manual page 1410

Low-power universal asynchronous receiver transmitter (LPUART)
Bits 31:9 Reserved, must be kept at reset value.
Bits 8:0 TDR[8:0]: Transmit data value
Note: This register must be written only when TXE=1.
1410/1830
Contains the data character to be transmitted.
The TDR register provides the parallel interface between the internal bus and the output
shift register (see Figure
When transmitting with the parity enabled (PCE bit set to 1 in the LPUART_CR1 register),
the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect
because it is replaced by the parity.
DocID024597 Rev 5
406).
RM0351