ST STM32L4 5 Series Reference Manual page 1444

Serial peripheral interface (SPI)
Bits 3:2 Reserved, must be kept at reset value.
Bit 1 TXE: Transmit buffer empty
Bit 0 RXNE: Receive buffer not empty
42.6.4 SPI data register (SPIx_DR)
Address offset: 0x0C
Reset value: 0x0000
15 14 13
rw rw rw
Bits 15:0 DR[15:0]: Data register
Data received or to be transmitted
The data register serves as an interface between the Rx and Tx FIFOs. When the data
register is read, RxFIFO is accessed while the write to data register accesses TxFIFO (See
Section 42.4.9: Data transmission and reception
Note: Data is always right-aligned. Unused bits are ignored when writing to the register, and
42.6.5 SPI CRC polynomial register (SPIx_CRCPR)
Address offset: 0x10
Reset value: 0x0007
15 14 13
rw rw rw
Bits 15:0 CRCPOLY[15:0]: CRC polynomial register
This register contains the polynomial for the CRC calculation.
The CRC polynomial (0007h) is the reset value of this register. Another polynomial can be
configured as required.
Note: The polynomial value should be odd only. No even value is supported.
1444/1830
0: Tx buffer not empty
1: Tx buffer empty
0: Rx buffer empty
1: Rx buffer not empty
12 11 10 9
rw rw rw rw
read as zero when the register is read. The Rx threshold setting must always
correspond with the read access currently used.
12 11 10 9
rw rw rw rw
8 7 6
DR[15:0]
rw rw rw
procedures).
8 7 6
CRCPOLY[15:0]
rw rw rw
DocID024597 Rev 5
5 4 3 2
rw rw rw rw
5 4 3 2
rw rw rw rw
RM0351
1 0
rw rw
1 0
rw rw