Figure 477. Swpmi Block Diagram - ST STM32L4 5 Series Reference Manual

RM0351
44.3 SWPMI functional description
44.3.1 SWPMI block diagram
Refer to the bit SWPMI1SEL in
register (RCC_CCIPR)
Note: In order to support the exit from Stop mode by a RESUME by slave, it is mandatory to select
HSI16 for SWPCLK. If this feature is not required, PCLK1 can be selected, and SWPMI
must be disabled before entering the Stop mode.
44.3.2 SWP initialization and activation
The initialization and activation will set the SWPMI_IO state from low to high.
For Class B, i.e. V
1. clear the SWP_CLASS bit in SWPMI_OR register,
2. configure SWPMI_IO as alternate function (refer to
(GPIO)) to enable the SWPMI_IO transceiver,
3. wait for t
4. set SWPACT bit in SWPMI_CR register to ACTIVATE the SWP i.e. to move from
DEACTIVATED to SUSPENDED.
For Class C, i.e. V
1. set the SWP_CLASS bit in SWPMI_OR register,
2. configure SWPMI_IO as alternate function (refer to
(GPIO)) to enable the SWPMI_IO transceiver,
3. set SWPACT bit in SWPMI_CR register to ACTIVATE the SWP i.e. to move from
DEACTIVATED to SUSPENDED.

Figure 477. SWPMI block diagram

Section 6.4.28: Peripherals independent clock configuration
to select the SWPCLK (SWPMI core clock source).
is in the range [2.70 V to 3.30 V], the procedure is the following:
DD
Max (refer to product datasheet),
SWPSTART
is in the range [1.62 V to 1.98 V], the procedure is the following:
DD
DocID024597 Rev 5
Single Wire Protocol Master Interface (SWPMI)
Section 8: General-purpose I/Os
Section 8: General-purpose I/Os
1493/1830
1517