ST STM32L4 5 Series Reference Manual page 1487

RM0351
Bit 3 FREQ: FIFO request.
This bit is read only.
0: No FIFO request.
1: FIFO request to read or to write the SAI_xDR.
The request depends on the audio block configuration:
– If the block is configured in transmission mode, the FIFO request is related to a write request
operation in the SAI_xDR.
– If the block configured in reception, the FIFO request related to a read request operation from the
SAI_xDR.
This flag can generate an interrupt if FREQIE bit is set in SAI_xIM register.
Bit 2 WCKCFG: Wrong clock configuration flag.
This bit is read only.
0: Clock configuration is correct
1: Clock configuration does not respect the rule concerning the frame length specification defined in
Section 43.3.6: Frame synchronization
This bit is used only when the audio block operates in master mode (MODE[1] = 0) and NODIV = 0.
It can generate an interrupt if WCKCFGIE bit is set in SAI_xIM register.
This flag is cleared when the software sets CWCKCFG bit in SAI_xCLRFR register.
Bit 1 MUTEDET: Mute detection.
This bit is read only.
0: No MUTE detection on the SD input line
1: MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio
frame
This flag is set if consecutive 0 values are received in each slot of a given audio frame and for a
consecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register).
It can generate an interrupt if MUTEDETIE bit is set in SAI_xIM register.
This flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register.
Bit 0 OVRUDR: Overrun / underrun.
This bit is read only.
0: No overrun/underrun error.
1: Overrun/underrun error detection.
The overrun and underrun conditions can occur only when the audio block is configured as a
receiver and a transmitter, respectively.
It can generate an interrupt if OVRUDRIE bit is set in SAI_xIM register.
This flag is cleared when the software sets COVRUDR bit in SAI_xCLRFR register.
43.5.8 Clear flag register (SAI_ACLRFR / SAI_BCLRFR)
Address offset: block A: 0x01C
Address offset: block B: 0x03C
Reset value: 0x0000 0000
31 30 29 28 27
Res. Res. Res. Res. Res. Res.
15 14 13 12 11
Res. Res. Res. Res. Res. Res.
26 25 24 23
Res. Res. Res.
10 9 8 7
Res. Res. Res. CLFSDET CAFSDET CCNRDY
DocID024597 Rev 5
(configuration of FRL[7:0] bit in the SAI_xFRCR register)
22 21 20
Res. Res. Res.
6 5 4
w w w
Serial audio interface (SAI)
19 18 17
Res. Res. Res.
3 2 1
CMUTE
Res. CWCKCFG
DET
w w
1487/1830
16
Res.
0
COVRUD
R
w
1490