ST STM32L4 5 Series Reference Manual page 1402

Low-power universal asynchronous receiver transmitter (LPUART)
41.7.3 Control register 3 (LPUART_CR3)
Address offset: 0x08
Reset value: 0x0000
31 30 29
Res. Res. Res. Res.
15 14 13
OVR
DEP DEM DDRE
DIS
rw rw rw
Bits 31:24 Reserved, must be kept at reset value.
Bit 23 UCESM: LPUART Clock Enable in Stop mode.
Bit 22 WUFIE: Wakeup from Stop mode interrupt enable
Note: WUFIE must be set before entering in Stop mode.
Bits 21:20 WUS[1:0]: Wakeup from Stop mode interrupt flag selection
Note: If the LPUART does not support the wakeup from Stop feature, this bit is reserved and
Bits 19:16 Reserved, must be kept at reset value.
Bit 15 DEP: Driver enable polarity selection
Bit 14 DEM: Driver enable mode
1402/1830
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. CTSIE CTSE
rw rw rw
This bit is set and cleared by software.
0: LPUART Clock is disabled in STOP mode.
1: LPUART Clock is enabled in STOP mode.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An LPUART interrupt is generated whenever WUF=1 in the LPUART_ISR register
The WUF interrupt is active only in Stop mode.
If the LPUART does not support the wakeup from Stop feature, this bit is reserved and
forced by hardware to '0'.
This bit-field specify the event which activates the WUF (wakeup from Stop mode flag).
00: WUF active on address match (as defined by ADD[7:0] and ADDM7)
01:Reserved.
10: WUF active on Start bit detection
11: WUF active on RXNE.
This bit field can only be written when the LPUART is disabled (UE=0).
forced by hardware to '0'.
0: DE signal is active high.
1: DE signal is active low.
This bit can only be written when the LPUART is disabled (UE=0).
This bit allows the user to activate the external transceiver control, through the DE signal.
0: DE function is disabled.
1: DE function is enabled. The DE signal is output on the RTS pin.
This bit can only be written when the LPUART is disabled (UE=0).
DocID024597 Rev 5
24 23 22 21
Res. UCESM WUFIE
rw rw rw
8 7 6
RTSE DMAT DMAR Res.
rw rw rw
20 19 18
WUS[2:0] Res. Res.
rw
5 4 3 2
HD
Res. Res.
SEL
rw
RM0351
17 16
Res. Res.
1 0
Res. EIE
rw