Device Descriptions - Mitsubishi Electric Melsec Q Series Programming Manual

5 OPERATION CONTROL PROGRAMS

5.2 Device Descriptions

16-bit
integer type
Data register Dn
Link register Wn
Special register SDn
Motion register #n
Multiple CPU
U \Gn
area device
Coasting timer —
(Note-1): The range of "2000 to 2255" cannot be specified indirectly.
(Note-2):
(Note-3): "p" indicates the user setting area points of the Multiple CPU high speed transmission area for each CPU.
Word and bit device descriptions are shown below.
(1) Word device descriptions
Device descriptions
32-bit
integer type
("n" is even No.)
DnL
WnL
SDnL
#nL
(Note-2) (Note-2)
U \GnL
FT
= CPU No. (CPU No.1: 3E0, CPU No.2: 3E1, CPU No.3: 3E2, CPU No.4: 3E3). A CPU No. that
exceeds the number of CPUs in the Multiple CPU system cannot be set.
(a) For differentiation, the 32-bit floating-point type is ended by L and the 64-bit
floating-point type by F (":F" for the link register).
(b) For the 32-bit integer type and 64-bit floating-point type, specify the device
number with an even number. (It cannot be set as an odd number.)
(c) The coasting timer FT is incremented per 888[µs]. (The coasting timer is a
32-bit integer type.)
Ver.! : Refer to Section 1.3 for the software version that supports this function.
Q173DSCPU/Q172DSCPU
64-bit
floating-point
type SV13
("n" is even No.)
DnF 0 to 8191
Wn:F
SDnF
#nF
(Note-2)
U \GnF
—
5 - 9
Device No. (n) specified ranges
SV22
Advanced
Virtual mode
synchronous
switching
control
method
Ver.!
method
0 to 19823
0 to 1FFF
(Note-1)
0 to 2255
0 to 12287
(Note-3)
10000 to (10000+p-1)
—
Q173DCPU(-S1)/
Q172DCPU(-S1)
0 to 8191