Mitsubishi Electric Melsec Q Series Programming Manual page 173

3 MOTION DEDICATED PLC INSTRUCTION
[Operation]
Sequence program
DP.DDRD instruction
CPU dedicated transmission
(0.88ms cycle)
Target CPU DP.DDRD
accept processing
Self CPU storing device
(D1)
Complete device (D2+0)
Status display device (D2+1)
at the completion
(5) There is a limitation for number of simultaneous instruction execution/
simultaneous acceptance in the Motion dedicated PLC instruction.
(Refer to Section 3.3 (2).)
Exchange a large amount of data through the CPU shared memory.
OUT
(D1)
Device memory
D0
D9
Outline operation between CPUs at the DP.DDRD instruction execution is shown
below.
DP.DDRD
ON execution
Request data set
Transfer
0.88ms
(n1)
3E1H
Read
(S1+1)
10 words
END
Transfer
Response
data set
DP.DDRD accept
processing
3 - 62
(S2)
Device memory
W10
(S1+1)
10 words
W19
END END
Set
ON
ON : Abnormal completion only
1 scan