Watch Mode - Fujitsu F2MC-8L Series Hardware Manual

CHAPTER 3 CPU
3.7.4

Watch Mode

This section describes operations in watch mode.
Operations in Watch Mode
Changing to watch mode
Watch mode stops the CPU and the operating clock for major peripheral circuits. The CPU can
enter this mode only when it is in subclock mode (with the main clock stopping oscillation).
Watch mode maintains the contents of registers and RAM, which they have immediately before
the CPU enters the mode, and stops all the functions except the watch prescaler (watch
interrupt), external interrupt circuit, and some subclock-based functions. This mode can hold
data at extremely low power consumption.
The CPU enters watch mode when the watch bit (TMD) in the standby control register (STBC) is
set to "1" in subclock mode (SYCC: SCS = "0") set by the system clock select bit in the system
clock control register.
When the CPU enters watch mode, the external pins hold the current states if the pin state
specification bit (SPL) in the standby control register (STBC) is "0". If the bit is "1", the pins are
placed in a high impedance state (those pins for which the pull-up resistor option has been
selected become "H" level).
If an interrupt request has been generated when "1" is written to the TMD bit, the write attempt
is ignored and the CPU continues execution of instructions without entering watch mode (the
CPU does not enter watch mode even after processing the interrupt request).
Wake-up from watch mode
A reset, watch interrupt, or external interrupt wakes up the CPU from watch mode.
If a reset occurs in watch mode on the product with the power-on reset function, the CPU
performs reset operation after taking the main clock oscillation stabilization delay time.
If a reset occurs in watch mode on the product without the power-on reset function, the CPU
does not require the oscillation stabilization delay time. The reset initializes pin states.
If an interrupt request at an interrupt priority level higher than "11" is issued from the watch
prescaler or external interrupt circuit in watch mode, the CPU wakes up from watch mode,
regardless of the interrupt enable flag (CCR: I) and interrupt level bits (CCR: IL1, IL0) in the
CPU. In watch mode, only watch interrupt or external interrupt requests can occur because
most peripheral functions other than the watch prescaler are stopped.
After waking up from watch mode, the CPU performs normal interrupt operation. When the
interrupt request is acceptable, the CPU performs the interrupt processing. If the interrupt
request is not acceptable, the CPU executes processing from the instruction following the
instruction executed immediately before entering watch mode.
When the CPU wakes up from watch mode, some peripheral functions resume operation.
Accordingly, the first interval time based on the interval timer function, for example, is
indeterminate. Therefore, initialize each peripheral function after waking up from watch mode.
80