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CXD5602 User Manual
CXD5602 User Manual
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  • Page 1 CXD5602 User Manual CXD5602 User Manual -1/1010-...
  • Page 2: Table Of Contents

    Table Contents ............................... 10 Introduction ..............................31 Introduction ............................. 31 Notation ..............................31 1.2.1 Notation of numerical value ......................31 CXD5602 Outline ............................33 Introduction ............................. 33 Features ..............................33 Block Diagram ............................36 Architecture Overview ..........................37 CPU Processor ............................38 2.5.1...
  • Page 3 CXD5602 User Manual 3.2.2 Function List ............................ 86 3.2.3 Function Specification Outlines ....................... 87 3.2.4 Detailed Function and Control Specification ................... 89 Interrupt ..............................112 3.3.1 Overview and Features ........................112 3.3.2 Register Descriptions ........................113 PMU (Power Management Unit) ......................116 3.4.1...
  • Page 4 CXD5602 User Manual SCU (Sensor Control Unit) ........................243 3.9.1 SCU Overview and Features ......................243 3.9.2 SCU Block Diagram ........................245 3.9.3 Memory Map ..........................246 3.9.4 Clock Control ..........................249 3.9.5 Power Supply Control ........................255 3.9.6 Interrupt ............................255 3.9.7...
  • Page 5 CXD5602 User Manual 3.18 USB ............................... 954 3.19 CIS I/F ..............................955 3.20 2D Graphics ............................955 3.21 ADC ............................... 956 3.21.1 ADC Overview ..........................956 3.21.2 ADC Block Diagram ........................957 3.21.3 Memory Map ..........................957 3.21.4 Power Supply Control ........................958 3.21.5...
  • Page 6 CXD5602 User Manual Figure Contents Figure Block Diagram-1 CXD5602 Block Diagram ....................36 Figure Memory Mapping-2 Memory Map of the SYSIOP, GNSS, and APP ............40 Figure Clock and Reset-3 Clock Diagram ....................... 47 Figure Power Management-4 Power Domain Layers ....................48 Figure Power Management-5 CXD5602 Power Domain ..................
  • Page 7 CXD5602 User Manual Figure PMU (Power Management Unit)-31 PMU Clock System ................. 125 Figure PMU (Power Management Unit)-32 Sleep/Wakeup Control Flow of the Application Processor ..... 157 Figure Clock and Reset (Clock Reset Generator)-33 CRG Control Area within Overall Clock Scheme ..... 159 Figure Clock and Reset (Clock Reset Generator)-34 CRG Clock Scheme ............
  • Page 8 CXD5602 User Manual Figure SCU (Sensor Control Unit)-69 Sequencer Overall Image ................278 Figure SCU (Sensor Control Unit)-70 Sequencer Process Flow (Example) ............278 Figure SCU (Sensor Control Unit)-71 Overall Data Flow (excluding Data Duplication Function) ...... 279 Figure SCU (Sensor Control Unit)-72 Startup Control ..................280 Figure SCU (Sensor Control Unit)-73 External Bus Transaction Generation ............
  • Page 9 CXD5602 User Manual Figure APP-107 Input-Output Addresses of Address Converter ................919 Figure APP-108 Address Conversion Operation Scheme ..................920 Figure APP-109 Example of Address Conversion: Conversion of Bit Assignment for ADSP0 ......923 Figure APP-110 Example of Address Conversion: Conversion Address Map for ADSP0 and ADSP1 ....923 Figure APP-111 Success Case 1 of Exclusive Access ...................
  • Page 10 CXD5602 User Manual Table Contents Table Notation-1 Notation of Numerical Value ...................... 31 Table Memory Mapping-2 Memory Mapping of the SYSIOP Block (SYS Window) ..........41 Table Memory Mapping-3 Memory Mapping of the APP Block (APP Window) ..........42 Table Power Management-4 Power Supply States ....................51 Table I/O Configuration-5 Function List .........................
  • Page 11 CXD5602 User Manual Table Interrupt-32 List of Interrupt Registers of Application Processor ............... 113 Table Interrupt-33 Interrupt Factor Registers of Application Processor ............... 113 Table PMU (Power Management Unit)-34 Power Supply States................120 Table PMU (Power Management Unit)-35 The Setting of the Power Supply in “Reset” State and After Changing to “Normal”...
  • Page 12 CXD5602 User Manual Table I2C-74 XOSC (26 MHz), High Performance Mode ..................213 Table I2C-75 XOSC (26 MHz), Low Power Mode ....................213 Table I2C-80 I2C0 and I2C1 Register List ......................214 Table I2C-81 I2C2 Register List ........................... 216 Table I2C-82 I2C4 Register List ........................... 218 Table DMAC-83 DMA Request Bit Assignment ....................
  • Page 13 CXD5602 User Manual Table SCU (Sensor Control Unit)-117 ........................320 Table SCU (Sensor Control Unit)-118 ........................321 Table SCU (Sensor Control Unit)-119 ........................322 Table SCU (Sensor Control Unit)-120 ........................323 Table SCU (Sensor Control Unit)-121 ........................326 Table SCU (Sensor Control Unit)-122 ........................327 Table SCU (Sensor Control Unit)-123 ........................
  • Page 14 CXD5602 User Manual Table SCU (Sensor Control Unit)-156 ........................361 Table SCU (Sensor Control Unit)-157 ........................361 Table SCU (Sensor Control Unit)-158 ........................362 Table SCU (Sensor Control Unit)-159 ........................363 Table SCU (Sensor Control Unit)-160 ........................363 Table SCU (Sensor Control Unit)-161 ........................364 Table SCU (Sensor Control Unit)-162 ........................
  • Page 15 CXD5602 User Manual Table SCU (Sensor Control Unit)-195 ........................382 Table SCU (Sensor Control Unit)-196 ........................383 Table SCU (Sensor Control Unit)-197 ........................383 Table SCU (Sensor Control Unit)-198 ........................384 Table SCU (Sensor Control Unit)-199 ........................384 Table SCU (Sensor Control Unit)-200 ........................385 Table SCU (Sensor Control Unit)-201 ........................
  • Page 16 CXD5602 User Manual Table SCU (Sensor Control Unit)-234 ........................406 Table SCU (Sensor Control Unit)-235 ........................406 Table SCU (Sensor Control Unit)-236 ........................407 Table SCU (Sensor Control Unit)-237 ........................407 Table SCU (Sensor Control Unit)-238 ........................408 Table SCU (Sensor Control Unit)-239 ........................408 Table SCU (Sensor Control Unit)-240 ........................
  • Page 17 CXD5602 User Manual Table SCU (Sensor Control Unit)-273 ........................455 Table SCU (Sensor Control Unit)-274 ........................456 Table SCU (Sensor Control Unit)-275 ........................457 Table SCU (Sensor Control Unit)-276 ........................457 Table SCU (Sensor Control Unit)-277 ........................458 Table SCU (Sensor Control Unit)-278 ........................459 Table SCU (Sensor Control Unit)-279 ........................
  • Page 18 CXD5602 User Manual Table SCU (Sensor Control Unit)-312 ........................488 Table SCU (Sensor Control Unit)-313 ........................488 Table SCU (Sensor Control Unit)-314 ........................489 Table SCU (Sensor Control Unit)-315 ........................490 Table SCU (Sensor Control Unit)-316 ........................491 Table SCU (Sensor Control Unit)-317 ........................492 Table SCU (Sensor Control Unit)-318 ........................
  • Page 19 CXD5602 User Manual Table SCU (Sensor Control Unit)-351 ........................529 Table SCU (Sensor Control Unit)-352 ........................529 Table SCU (Sensor Control Unit)-353 ........................530 Table SCU (Sensor Control Unit)-354 ........................531 Table SCU (Sensor Control Unit)-355 ........................532 Table SCU (Sensor Control Unit)-356 ........................533 Table SCU (Sensor Control Unit)-357 ........................
  • Page 20 CXD5602 User Manual Table SCU (Sensor Control Unit)-390 ........................560 Table SCU (Sensor Control Unit)-391 ........................561 Table SCU (Sensor Control Unit)-392 ........................561 Table SCU (Sensor Control Unit)-393 ........................562 Table SCU (Sensor Control Unit)-394 ........................563 Table SCU (Sensor Control Unit)-395 ........................564 Table SCU (Sensor Control Unit)-396 ........................
  • Page 21 CXD5602 User Manual Table SCU (Sensor Control Unit)-429 ........................590 Table SCU (Sensor Control Unit)-430 ........................591 Table SCU (Sensor Control Unit)-431 ........................591 Table SCU (Sensor Control Unit)-432 ........................592 Table SCU (Sensor Control Unit)-433 ........................593 Table SCU (Sensor Control Unit)-434 ........................594 Table SCU (Sensor Control Unit)-435 ........................
  • Page 22 CXD5602 User Manual Table SCU (Sensor Control Unit)-468 ........................618 Table SCU (Sensor Control Unit)-469 ........................619 Table SCU (Sensor Control Unit)-470 ........................620 Table SCU (Sensor Control Unit)-471 ........................620 Table SCU (Sensor Control Unit)-472 ........................621 Table SCU (Sensor Control Unit)-473 ........................621 Table SCU (Sensor Control Unit)-474 ........................
  • Page 23 CXD5602 User Manual Table SCU (Sensor Control Unit)-507 ........................648 Table SCU (Sensor Control Unit)-508 ........................649 Table SCU (Sensor Control Unit)-509 ........................650 Table SCU (Sensor Control Unit)-510 ........................651 Table SCU (Sensor Control Unit)-511 ........................651 Table SCU (Sensor Control Unit)-512 ........................652 Table SCU (Sensor Control Unit)-513 ........................
  • Page 24 CXD5602 User Manual Table SCU (Sensor Control Unit)-546 ........................681 Table SCU (Sensor Control Unit)-547 ........................681 Table SCU (Sensor Control Unit)-548 ........................682 Table SCU (Sensor Control Unit)-549 ........................683 Table SCU (Sensor Control Unit)-550 ........................684 Table SCU (Sensor Control Unit)-551 ........................685 Table SCU (Sensor Control Unit)-552 ........................
  • Page 25 CXD5602 User Manual Table SCU (Sensor Control Unit)-585 ........................713 Table SCU (Sensor Control Unit)-586 ........................714 Table SCU (Sensor Control Unit)-587 ........................715 Table SCU (Sensor Control Unit)-588 ........................716 Table SCU (Sensor Control Unit)-589 ........................716 Table SCU (Sensor Control Unit)-590 ........................717 Table SCU (Sensor Control Unit)-591 ........................
  • Page 26 CXD5602 User Manual Table SCU (Sensor Control Unit)-624 ........................746 Table SCU (Sensor Control Unit)-625 ........................746 Table SCU (Sensor Control Unit)-626 ........................747 Table SCU (Sensor Control Unit)-627 ........................748 Table SCU (Sensor Control Unit)-628 ........................749 Table SCU (Sensor Control Unit)-629 ........................750 Table SCU (Sensor Control Unit)-630 ........................
  • Page 27 CXD5602 User Manual Table SCU (Sensor Control Unit)-663 ........................778 Table SCU (Sensor Control Unit)-664 ........................779 Table SCU (Sensor Control Unit)-665 ........................780 Table SCU (Sensor Control Unit)-666 ........................781 Table SCU (Sensor Control Unit)-667 ........................781 Table SCU (Sensor Control Unit)-668 ........................782 Table SCU (Sensor Control Unit)-669 ........................
  • Page 28 CXD5602 User Manual Table SCU (Sensor Control Unit)-702 ........................807 Table SCU (Sensor Control Unit)-703 ........................808 Table SCU (Sensor Control Unit)-704 ........................809 Table SCU (Sensor Control Unit)-705 ........................809 Table SCU (Sensor Control Unit)-706 ........................810 Table SCU (Sensor Control Unit)-707 ........................811 Table SCU (Sensor Control Unit)-708 Power Supply Control Power ON ............
  • Page 29 CXD5602 User Manual Table SPI-749 SPI0 register Descriptions ......................876 Table SPI-750 SPI3 Register List .......................... 878 Table SPI-751 SPI3 Register Descriptions ......................878 Table SPI-752 SPI4 Register List .......................... 880 Table SPI-753 SPI5 Register List .......................... 882 Table UART-758 XOSC (26 MHz), High Performance Mode ................884 Table UART-759 XOSC (26 MHz), Low Power Mode ..................
  • Page 30 CXD5602 User Manual Table ADC-812 Power Supply Information ......................958 Table ADC-813 Clock Summary .......................... 959 Table ADC-814 Clock Control Register List ......................960 Table ADC-815 Input Clock Selection ........................961 Table ADC-816 Main Reset Control ........................962 Table ADC-817 Gain Control of the HPADC ....................... 963 Table ADC-818 ADC Sampling Frequency Estimation ..................
  • Page 31: Introduction

    CXD5602 User Manual Introduction Introduction This manual is intended for CXD5602 users. Notation 1.2.1 Notation of numerical value The table below shows notation of numerical values used in this document. Table Notation-1 Notation of Numerical Value Base Notation Example Base 16 adds prefixed "0x"...
  • Page 32 CXD5602 User Manual The notation examples are as follows.  5-bit unsigned signal with integer number is noted as U5.0.  5-bit unsigned signal with decimal point [1].[0] position is noted as U4.1.  5-bit unsigned signal with decimal point [-1].[-2] position is noted as U6.-1.
  • Page 33: Cxd5602 Outline

    CXD5602 User Manual CXD5602 Outline Introduction CXD5602GF/GG is a 32 bit RISC low power microprocessor solution for wearable applications. It is based on the ® ® ® ® Cortex -M4 processor with FPU 32 bit RISC and It integrates Arm...
  • Page 34 CXD5602 User Manual BitBLT, Rotate, Scaling, Blender  Connectivity/Storage Interface On-chip USB2.0 Device supported eMMC 4.41 for eMMC Device SD3.0 Host Controller interface SPI and SDIO support for external Wi-Fi transceivers UART support for external Bluetooth transceivers Quad SPI-FLASH Interface ...
  • Page 35 CXD5602 User Manual Two channels 10 bit high performance ADC  Multi-GNSS Controller ® ® Cortex -M4 processor with FPU 32 bit RISC Operating frequency up to 98.208 MHz 64 KByte ROM 640 KByte SRAM CORDIC engine for GNSS support ...
  • Page 36: Block Diagram

    CXD5602 User Manual Block Diagram Figure Block Diagram-1 CXD5602 Block Diagram -36/1010-...
  • Page 37: Architecture Overview

    -M4 for the APP. The CXD5602 has a bus architecture using the Bus Matrix so that eight CPUs and the other bus masters can independently access to each slave, not affected by any bus traffic. By Round-robin arbitration inside the Bus Matrix, bus master need not to wait for a long time to access to slave even if access competition occurs.
  • Page 38: Cpu Processor

    CXD5602 User Manual CPU Processor 2.5.1 Application Processor ® The application processor integrates six Cortex -M4 processors with FPU to meet the requirements of wearable devices, which demand operation in low power and performance-optimized consumer applications with the ability ®...
  • Page 39 CXD5602 User Manual Boot from embedded ROM  It is used to download the program to either SPI-Flash memory or eMMC via one of the available interfaces (USB device, Configurable I/O<UART>, or the Host Interface<SPI, UART, and I2C>).  Processor system peripherals ...
  • Page 40: Memory Mapping

    CXD5602 User Manual Memory Mapping Overview of Memory Map Configuration Memory map is made up of three types of views. The “SYS View” can be referred from System and I/O Processor, the “GNSS View” can be referred from the GNSS DSP, and the “APP View” can be referred from Application Processor.
  • Page 41: Memory Map Of Each Block

    CXD5602 User Manual 2.6.1 Memory Map of Each Block For detailed address information of the SYSIOP block, the GNSS block, and each functional block, refer to the content of each functional block. Table Memory Mapping-2 Memory Mapping of the SYSIOP Block (SYS Window)
  • Page 42: Main Memory

    CXD5602 User Manual Table Memory Mapping-3 Memory Mapping of the APP Block (APP Window) Category Pheripheral Name Start Address End Address Size (4k bytes unit) Reserved Reserved 0x0C000000 0x0CFFFFFF SRAM SRAM (1.5M B) 0x0D000000 0x0D17FFFF 1.5M Reserved Reserved 0x0D180000 0x0DFFFFFF...
  • Page 43: System Memory

    The CXD5602 has five types of usable clock sources and is made up of main five clock domains in accordance -43/1010-...
  • Page 44 A variety of processors can dynamically select multiple usable clock source, and use most suitable clock frequency optimized for the operating conditions by using divider circuit architecture. The functions of clock and reset of the CXD5602 are described below. ...
  • Page 45 CXD5602 User Manual  System reset from Watchdog Timer (WDT)  It is a whole chip reset controlled by the WDT of the SYSCPU.  You can enable/disable whole chip reset controlled by the WDT with register setting. -45/1010-...
  • Page 46: Clock Architecture

    CXD5602 User Manual 2.7.2 Clock Architecture The figure below shows CX5602 clock diagram. The CXD5602 has main five clock domains according to functional blocks. Clock can be selected in accordance with the operating conditions of each functional block.  Always On ...
  • Page 47 CXD5602 User Manual Application Domain 163MHz(High performance mode) / 40MHz(Low Power mode) Application Divider Processor APP Bus Divider Divider Peripheral CIS I/F 49.104MHz Divider SDIO 2D Graphics 49.104MHz eMMC Divider Divider AUDIO MCLK 24.576kHz System and IOP Domain 100MHz(High performance mode)
  • Page 48: Power Management

    2.8.1 Overview The CXD5602 has a large power domain, which is divided into 11 domains. It performs ON control of necessary functions only, while performing OFF control of the unnecessary ones, thereby reducing the power consumption. Additionally, the SRAM or analog circuits such as the ADC within the power supply domains enable individual power supply control.
  • Page 49 DMAC (Clefia) SRAM Engine (128KB) (40KB) × (1KB) Figure Power Management-5 CXD5602 Power Domain The following describes the functions of each power domain. Application Domain  PWD_APP  All components of Application Domain  Including 1.5 MByte SRAM in Application memory and Application Multi-layer Bus ...
  • Page 50 CXD5602 User Manual  Audio Codec System and IOP Domain  PWD_SYSIOP  System and IOP Domain  Excluding 256 KByte SRAM in System and I/O Processor Memory  PWD_SYSIOP_SUB  Configurable I/O (I2C, SPI, UART) Interface  SPI-FLASH Interface ...
  • Page 51: Power Supply States

    Power supply state Description Power Off Both the CXD5602 (referred to as “the LSI” hereinafter) and the CXD5247 are OFF. Deep Sleep The LSI is OFF and the CXD5247 is ON. In this state, the RTC of the CXD5247 is counting, and time information can be obtained from the CXD5247 after the LSI is started.
  • Page 52 CXD5602 User Manual State: Power OFF CXD5247 CXD5602 System and Application GNSS Sensor State: Normal (Domain ON) IOP Domain Domain Domain Domain (PMIC) (Transition to each state is possible.) CXD5602 System and Application GNSS Sensor IOP Domain ON Domain ON...
  • Page 53: Function Details

    CXD5602 User Manual Function Details I/O Configuration 3.1.1 Outline I/O Configuration switches between HOST I/F select function and Serial Wire Debug (SWD) function, and controls Pin Multiplexer. 3.1.2 Function List Table I/O Configuration-5 shows I/O Configuration function list. Table I/O Configuration-5 Function List...
  • Page 54: Switching Between Host I/f Select Function And Swd Function

    CXD5602 User Manual 3.1.3 Switching between HOST I/F Select Function and SWD Function Once clock is provided to this block after Power-on Reset (POR) release, values of pin SYSTEM0 and pin SYSTEM1 are held inside. A HOST I/F is selected from I2C, SPI, or UART in accordance with the held values.
  • Page 55: Pin Multiplexer

    CXD5602 User Manual 3.1.4 Pin Multiplexer To each pin of this LSI, Pin Multiplexer can assign a role selecting from up to four options. Multiple roles cannot be played at a time. Not only General Purpose Input/Output (GPIO) mode controlled by register, but also...
  • Page 56 CXD5602 User Manual 0x04100844 IO_SPI0_CS_X IOCELL setting for pin P16_00 0x01010100 0x04100848 IO_SPI0_SCK IOCELL setting for pin P16_01 0x01010100 0x0410084C IO_SPI0_MOSI IOCELL setting for pin P17_00 0x01010100 0x04100850 IO_SPI0_MISO IOCELL setting for pin P17_01 0x01010100 0x04100854 IO_SPI1_CS_X IOCELL setting for pin P18_00...
  • Page 57 CXD5602 User Manual 0x041008E4 IO_IS_VSYNC IOCELL setting for pin P1m_01 0x01010100 0x041008E8 IO_IS_HSYNC IOCELL setting for pin P1m_02 0x01010100 0x041008EC IO_IS_DATA0 IOCELL setting for pin P1m_03 0x01010100 0x041008F0 IO_IS_DATA1 IOCELL setting for pin P1m_04 0x01010100 0x041008F4 IO_IS_DATA2 IOCELL setting for pin P1m_05...
  • Page 58 CXD5602 User Manual 0x04100974 IO_I2S0_BCK IOCELL setting for pin P1v_00 0x01010100 0x04100978 IO_I2S0_LRCK IOCELL setting for pin P1v_01 0x01010100 0x0410097C IO_I2S0_DATA_IN IOCELL setting for pin P1v_02 0x01010100 0x04100980 IO_I2S0_DATA_OUT IOCELL setting for pin P1v_03 0x01010100 0x04100984 IO_I2S1_BCK IOCELL setting for pin P1w_00...
  • Page 59 CXD5602 User Manual 3.1.4.2 Register Descriptions 3.1.4.2.1 Registers for selecting a role of the I/O pins belonging to SYS group Table I/O Configuration-10 shows registers for selecting a role of the I/O pins belonging to SYS group. Setting examples are explained in “3.1.4.3 Function Details”.
  • Page 60 CXD5602 User Manual Table I/O Configuration-11 shows pin functions selected by IOCSYS_IOMD0 and IOSYS_IOMD1. Table I/O Configuration-11 Table of Role Selection for I/O Pins Belonging to SYS Group Register Register Setting value Name Name P10_00 IOCSYS_IOMD0.I2C4 GPIO I2C_BCK GPIO GPIO...
  • Page 61 CXD5602 User Manual P1i_00 IOCSYS_IOMD1.SPI3 GPIO SPI3_SCK Reserved Reserved P1i_01 GPIO SPI3_MOSI Reserved Reserved P1i_02 GPIO SPI3_MISO Reserved Reserved P1j_00 IOCSYS_IOMD1.I2C0 GPIO I2C0_BCK Reserved Reserved P1j_01 GPIO I2C0_BDT Reserved Reserved P1k_00 IOCSYS_IOMD1.PWMA GPIO PWM0 Reserved Reserved P1k_01 GPIO PWM1 GPIO...
  • Page 62 CXD5602 User Manual 3.1.4.2.2 Register for selecting a role of the I/O pins belonging to APP group Table I/O Configuration-12 shows registers for selecting a role of the I/O pins belonging to APP group. Setting examples are explained in “3.1.4.3 Function Details”.
  • Page 63 CXD5602 User Manual Table I/O Configuration-13 shows pin functions selected by IOCAPP_IOMD. Table I/O Configuration-13 Table of Role Selection for the I/O Pins Belonging to APP Group Pin Name Register Name Register Setting value P1m_00 IOCAPP_IOMD.IS GPIO IS_CLK GPIO GPIO...
  • Page 64 CXD5602 User Manual P1t_00 IOCAPP_IOMD.SDIOC GPIO SDIO_CMDDIR GPIO GPIO P1t_01 GPIO SDIO_DIR0 GPIO GPIO P1t_02 GPIO SDIO_DIR1_3 GPIO GPIO P1u_00 IOCAPP_IOMD.SDIOD GPIO SDIO_CLKI GPIO GPIO P1v_00 IOCAPP_IOMD.I2S0 GPIO I2S0_BCK Reserved GPIO P1v_01 GPIO I2S0_LRCK Reserved GPIO P1v_02 GPIO I2S0_DATA_IN Reserved...
  • Page 65 CXD5602 User Manual 3.1.4.2.3 IOCELL Control Register These registers set IOCELL of each I/O pin. Table I/O Configuration-14 shows overview of registers. Figure I/O Configuration-8 shows a visualized function inside IOCELL controlled by the parameter that is set by IOCELL control register.
  • Page 66 CXD5602 User Manual IOCELL.LOWEMI IOCELL.PDN IO_Configration IOCELL.PUP GPIO Regs Output Enable IOCSYS{0,1}.* IOCAPP.* Pull up State IO Pin Alternate Function Output Pull Dn State GPIO Regs Alternate Function Input IOCELL.ENZI Figure I/O Configuration-8 Visualized Function inside IOCELL Controlled by IOCELL Control Register...
  • Page 67 CXD5602 User Manual Table I/O Configuration-15 Correspondence Table of IOCELL Control Registers and Controllable I/O Pins Register Name Pin Name Register Name Pin Name Register Name Pin Name IO_I2C4_BCK P10_00 IO_I2C0_BCK P1j_00 IO_EMMC_DATA2 P1q_00 IO_I2C4_BDT P10_01 IO_I2C0_BDT P1j_01 IO_EMMC_DATA3 P1q_01...
  • Page 68 CXD5602 User Manual 3.1.4.2.4 I2S Output Control Register This register performs Output Enable setting when pin P1v_{00,01} and pin P1w_{00,01} are used as I2S I/F. I2S is operated in master mode or slave mode. When you use I2S in master mode, set it Output Enable to use P1v_{00,01} and pin P1w_{00,01} as output pin.
  • Page 69 CXD5602 User Manual 3.1.4.2.6 SDIO Input Control Register This register sets input values to IP (SDIO) inside the LSI when pin P1s_{00,01} is not used as SDIO function (when GPIO mode is selected). For function details, refer to “3.1.4.3.31 SDIO.”...
  • Page 70 CXD5602 User Manual Select GPIO(inout) Select SDIO_DATA0(inout) IO Configuration IO Configuration IOCAPP_IMOD.SDIOA=0 IOCAPP_IMOD.SDIOA=1 GPIO GPIO 0 1 2 3 0 1 2 3 SDIO SDIO SPI5 SPI5 IO_SDIO_DATA0.ENZI IO_SDIO_DATA0.ENZI Select SPI5_MOSI(output) IO Configuration IOCAPP_IMOD.SDIOA=2 GPIO 0 1 2 3 SDIO SPI5 IO_SDIO_DATA0.ENZI...
  • Page 71 CXD5602 User Manual 3.1.4.3.1 I2C4 The following are settings that pin P10_{00,01} is assigned I2C (for PMIC) role.  IO_I2C_BCK.ENZI=1  IO_I2C_BDT.ENZI=1  IOCSYS_IOMD0.I2C4=1 3.1.4.3.2 PMIC_INT The following are settings that pin P11_00 is assigned PMIC_INT role.  IO_PMIC_INT.ENZI=1 ...
  • Page 72 CXD5602 User Manual IO Configuration IOCSYS_IMOD0.PMIC_INT RTC0 GP_PMIC_INT.DIR OExtAlarm select PMIC_INT 0 1 2 3 PMIC_INT ExternalAlerm2 ExternalAlerm1 GP_PMIC_INT.OUT ExternalAlerm0 P11_00 RTC1 OExtAlarm GP_PMIC_INT.IN PMIC_INT ExternalAlerm2 ExternalAlerm1 ExternalAlerm0 OPEN IO_PMIC_INT.ENZI Interrupt to CPU (PMIC_INT) IOCSYS_IMOD0.RTC_IRQ_OUT GP_RTC_IRQ_OUT.DIR 0 1 2 3 GP_RTC_IRQ_OUT.OUT...
  • Page 73 In this mode, the pin P11_00 is used bidirectionally as RTC_IRQ_OUT output role, and as PMIC_INT (for RTC synchronization) input role. By using pins of both CXD5602 and PMIC connected to CXD5602 as Open Drain, the above two roles can be compatible without any dynamic I/O control.
  • Page 74 CXD5602 User Manual 3.1.4.3.4 RTC_IRQ_OUT The following is a setting that pin P12_00 is assigned RTC_IRQ_OUT role.  IOCSYS_IOMD0.RTC_IRQ_OUT=1 3.1.4.3.5 RTC_IRQ_OUT(Open Drain) The following is a setting that pin P12_00 is assigned RTC_IRQ_OUT role (Open Drain). The pin becomes to operate as Open Drain.
  • Page 75 CXD5602 User Manual 3.1.4.3.6 AP_CLK The following are settings that pin P13_00 is assigned AP_CLK role.  IO_AP_CLK.ENZI=1  IOCSYS_IOMD0.AP_CLK=1 3.1.4.3.7 PMU_WDT The following is a setting that pin P13_00 is assigned PMU_WDT role.  IOCSYS_IOMD0.AP_CLK=2 3.1.4.3.8 PMU_WDT (Open Drain) The following is a setting that pin P13_00 is assigned PMU_WDT (Open Drain) role.
  • Page 76 CXD5602 User Manual 3.1.4.3.12 UART1 The following are settings that pin P16_{00,01} are assigned UART role.  IO_SPI0_SCK.ENZI=1  IOCSYS_IOMD0.SPI0A=1 3.1.4.3.13 I2C2 The following are settings that pin P17_{00,01} are assigned I2C role.  IO_SPI0_MOSI.ENZI=1  IO_SPI0_MISO.ENZI=1  IOCSYS_IOMD0.SPI0B=1 3.1.4.3.14 SPI0 The following are settings that pin P16_{00,01} and P17_{00,01} are assigned SPI role.
  • Page 77 CXD5602 User Manual 3.1.4.3.16 SPI2 If the pin SYSTEM0 is Low and the pin SYSTEM1 is High when POR is released, pin P00_{00,01} and pin P01_{00,01} are assigned SPI role automatically. For this reason, usually SPI2 role cannot be set by registers.
  • Page 78 CXD5602 User Manual 3.1.4.3.18 I2C3 If the pin SYSTEM0 is Low and the pin SYSTEM1 is Low when POR is released, pin P00_{00,01} are assigned I2C role automatically. For this reason, usually I2C3 role cannot be set by registers. The following are settings to release roles assigned automatically by pin SYSTEM0 and pin SYSTEM1, and to newly assign pin P00_{00,01} I2C role for debugging.
  • Page 79 CXD5602 User Manual 3.1.4.3.23 SPI3 The following are settings that pin P1f_00, pin P1g_00, pin P1h_00, and pin P1i_{00,01,02} are assigned SPI role.  IO_SPI3_MISO.ENZI=1  IOCSYS_IOMD1.SPI3_CS0_X=1  IOCSYS_IOMD1.SPI3_CS1_X=1  IOCSYS_IOMD1.SPI3_CS2_X=1  IOCSYS_IOMD1.SPI3=1 3.1.4.3.24 I2C0 The following are settings that pin P1j_{00,01} is assigned I2C role.
  • Page 80 CXD5602 User Manual 3.1.4.3.27 Image Sensor The following are settings that pin P1m_{00,01,02,03,04,05,06,07,08,09,10} are assigned Image Sensor role.  IO_IS_CLK.ENZI=1  IO_IS_VSYNC.ENZI=1  IO_IS_HSYNC.ENZI=1  IO_IS_DATA{0~7}.ENZI=1  IOCAPP_IOMD.IS=1 3.1.4.3.28 UART2(APP_UART) The following are settings that pin P1n_{00,01,02,03} are assigned UART role.
  • Page 81 CXD5602 User Manual 3.1.4.3.31 SDIO The following are settings that pin P1r_{00,01,02,03,04,05}, pin P1s{00,01}, pin P1t_{00,01,02}, and pin P1u_00 are assigned SDIO role.  IO_SIDO_CLK.ENZI=1  IO_SIDO_CMD.ENZI=1  IO_SIDO_DATA{0~3}.ENZI=1  IO_SIDO_CD.ENZI=1  IO_SIDO_WP.ENZI=1  IO_SIDO_CLKI.ENZI=1  IOCAPP_IOMD.SDIOA=1  IOCAPP_IOMD.SDIOB=1 ...
  • Page 82 CXD5602 User Manual IO Configuration IOCAPP_IMOD.SDIOA GP_SDIO_CLK.DIR 0 1 2 3 GP_SDIO_CLK.OUT SDIO_CLK P1r_00 SPI5_SCK GP_SDIO_CLK.IN SDIO_CLK SPI5_SCK OPEN IO_SDIO_CLK.ENZI SDIO IOCAPP_IMOD.SDIOD GP_SDIO_CLKI.DIR 0 1 2 3 GP_SDIO_CLKI.OUT P1u_00 GP_SDIO_CLKI.IN SDIO_CLKI OPEN OPEN IO_SDIO_CLKI.ENZI Figure I/O Configuration-13 SDIO CLK Input Schematic...
  • Page 83 CXD5602 User Manual While pin P1s_00 and pin P1s_01 are assigned GPIO role, CD/WP signal of internal IP (SDIO) can be set by using IOFIX_APP. Figure I/O Configuration-14 shows connecting diagram of CD/WP signal to SDIO IP. IO Configuration IOCAPP_IMOD.SDIOB GP_SDIO_CD.DIR...
  • Page 84 CXD5602 User Manual The following are settings that pin P1v_{00,01,02,03} are used as the I2S slave.  IO_IOOEN_APP.I2S0_BCK=1 (Output Disable)  IO_IOOEN_APP.I2S0_LRCK=1 (Output Disable)  IO_I2S0_BCK.ENZI=1 (Input Enable)  IO_I2S0_LRCK.ENZI=1 (Input Enable)  IO_I2S0_DATA_IN.ENZI=1 (Input Enable)  IOCAPP_IOMD.I2S0=1 3.1.4.3.33 I2S1 When you use a pin as I2S role, you need to select I2S role by using IOCAPP_IOMD, as well as decide in which mode I2S role should be played, master or slave.
  • Page 85 CXD5602 User Manual  IO_PDM_IN.ENZI=1 (Input Enable)  AUDIO_IF_SEL.PDM_CLK_SEL=0  IOCAPP_IOMD.PDM=1 The following are settings that pin P1y_{00,01,02} are assigned PDM_OUT role (MCK_DMIC output).  IO_PDM_IN.ENZI=1 (Input Enable)  AUDIO_IF_SEL.PDM_CLK_SEL=1  IOCAPP_IOMD.PDM=1 3.1.4.3.36 USB_VBUSINT The following are settings that pin P1z_00 is assigned USB_VBUSINT input role.
  • Page 86: General Purpose Input/output (gpio)

    CXD5602 User Manual General Purpose Input/Output (GPIO) 3.2.1 Outlines and Features In the chapter of GPIO, GPIO control, detection control, and pin selection for interrupt are explained. 3.2.2 Function List Table General Purpose Input/Output (GPIO)-19 Function List Function Name Description...
  • Page 87 CXD5602 User Manual 3.2.3 Function Specification Outlines 3.2.3.1 Function Block Diagrams Figure General Purpose Input/Output (GPIO)-15 shows entire functions of GPIO and Figure General Purpose Input/Output (GPIO)-16 shows Event Detect block inside GPIO function. I/O Function Pull-up/Pull-down Pull up/down, LOWEMI...
  • Page 88 CXD5602 User Manual Event Detect Wakeup factor (to PMU) RTC0 GNSS Internal signal detection SYSIOP_SUB Pos edge Pulse S et C lr HI F_DETECT_I2C _SLAVE INT_PMIC_I2CM Interrupt (to CPU/DSP) EXDEVICE[11:0] USBVBUS External signal detection USBVBUSN HVDD PMIC_INT Instant High Pulse...
  • Page 89 CXD5602 User Manual 3.2.4 Detailed Function and Control Specification 3.2.4.1 GPIO Control GPIO Control can be performed when I/O pins are set as GPIO mode. The GPIO mode can be set by using Pin Multiplexer register IOCSYS_IOMD{0,1} or IOCAPP_IOMD{0,1}. For details for setting GPIO mode, refer to Section 3.1.4 (Pin Multiplexer).
  • Page 90 CXD5602 User Manual Table General Purpose Input/Output (GPIO)-21 Correspondence of GPIO Control Registers to I/O Pins Register Name Pin Name Register Name Pin Name Register Name Pin Name GP_I2C4_BCK P10_00 GP_I2C0_BCK P1j_00 GP_EMMC_DATA2 P1q_00 GP_I2C4_BDT P10_01 GP_I2C0_BDT P1j_01 GP_EMMC_DATA3 P1q_01...
  • Page 91 CXD5602 User Manual GPIO Output Control 0/1 can be output to an I/O pin according to the control register setting. The status that a control register value is directly output to an I/O pin is called GPIO Output Control. Settings in GPIO Output Control are described below.
  • Page 92 CXD5602 User Manual GPIO Input Control Values that are input to I/O pins can be read out as the status registers. As for the inputs, the status registers can be read out without any special settings. This function is called “input control” in contrast to output control but actually the “input control”...
  • Page 93 CXD5602 User Manual 3.2.4.2 I/O Pin Selection In the chapter of I/O Pin Selection, how to select pins used as external interrupts is explained. I/O pins used as interrupts are classified into two groups: SYS group and APP group. You can select six pins each from both SYS group and APP group.
  • Page 94 CXD5602 User Manual Table General Purpose Input/Output (GPIO)-22 and Table General Purpose Input/Output (GPIO)-24 show registers that select I/O pins, Table General Purpose Input/Output (GPIO)-23 and Table General Purpose Input/Output (GPIO)-25 show selectable I/O pins. Initial value of a register is set as 63. In this case, no I/O pin is selected and an input value to the circuit for detecting interrupts or events is tied to “0”.
  • Page 95 CXD5602 User Manual Table General Purpose Input/Output (GPIO)-23 Correspondence of I/O Pins to Setting Values (SYS Group) Selected Setting Selected Setting Selected Setting Selected Setting Name Value Name Value Name Value Name Value - P10_00 P16_00 P1l_01 - - P10_01 P16_01 -...
  • Page 96 CXD5602 User Manual Table General Purpose Input/Output (GPIO)-25 Correspondence of I/O Pins to Setting Values (APP Group) Selected Setting Selected Setting Selected Setting Selected Setting Name Value Name Value Name Value Name Value P1m_00 P1o_01 P1s_01 P1y_02 P1m_01 P1o_02 P1t_00 P1z_00 -...
  • Page 97 CXD5602 User Manual 3.2.4.3 External Interrupt Selected I/O pins described in the section 3.2.4.2 and some other pins (refer to Table General Purpose Input/Output (GPIO)-27) can be communicated to SYSCPU and DSP as external interrupts with no changes. Besides, not only I/O pins’ values themselves can be communicated to SYSCPU and DSP, but information that an event has been detected (refer to 3.2.4.4) can be as well.
  • Page 98 CXD5602 User Manual Table General Purpose Input/Output (GPIO)-26 shows control registers for processing external interrupt signals. Table General Purpose Input/Output (GPIO)-26 External Interrupt Selection Address Register Bit Field Type Initial Description Name Name Value 0x04100468 PMU_WAKE_TRIG_ Reserved [31] Reserved CPUINTSEL0...
  • Page 99 CXD5602 User Manual APPGPI2 [18:16] Refer to SYSGPI3 Reserved [15] Reserved APPGPI1 [14:12] Refer to SYSGPI3 Reserved [11] Reserved APPGPI0 [10:8] Refer to SYSGPI3 Reserved Reserved SYSGPI5 [6:4] Refer to SYSGPI3 Reserved Reserved SYSGPI4 [2:0] Refer to SYSGPI3 0x04100470 PMU_WAKE_TRIG_...
  • Page 100 CXD5602 User Manual 3.2.4.4 Event Detection Control Event detection asserts when it detects that a signal meets conditions set for detection. It keeps the status until the control register clears the status. Event Detection Control can perform edge detection, level detection, and instant detection of external signals from I/O pins.
  • Page 101 CXD5602 User Manual Table General Purpose Input/Output (GPIO)-27 shows I/O pins that can be used for event detection. As for I/O pins that can be used for interrupt (refer to 3.2.4.2), bit-field names of interrupt factor registers are described in the “Interrupt Factor”...
  • Page 102 (6) Both Edge Detection (7) Both Edge Detection (This function removes information of event detection that is made when CXD5602 is reset and then the reset is released while the status of the I/O pin is High. That is because the input value of the I/O pin is not actually changed.)
  • Page 103 CXD5602 User Manual Figure General Purpose Input/Output (GPIO)-22 shows event detection timings of (0) to (5) of the above seven ways. RTC Clock External Signal (0) Instant High (1) Instant Low Always Event det ect (2) Level High (3) Level Low...
  • Page 104 CXD5602 User Manual SYSGPI3 [19] SYSGPI2 [18] SYSGPI1 [17] SYSGPI0 [16] HVDD_DET [15] HIF_UART_RXD [14] HIF_SPI_CS_X [13] HIF_SCL_LOW [12] Reserved [11:0] Reserved 0x04100474 PMU_WAKE_TRIG_ Reserved [31] Reserved INTDET0 SYSGPI3 [30:28] Selection of the way of detecting events 0: Instant H,...
  • Page 105 CXD5602 User Manual APPGPI4 [26:24] refer to SYSGPI3 Reserved [23] Reserved APPGPI3 [22:20] refer to SYSGPI3 Reserved [19] Reserved APPGPI2 [18:16] refer to SYSGPI3 Reserved [15] Reserved APPGPI1 [14:12] refer to SYSGPI3 Reserved [11] Reserved APPGPI0 [10:8] refer to SYSGPI3...
  • Page 106 CXD5602 User Manual 3.2.4.4.2 Status of Event Detection When an event is detected, a status register for event detection becomes High and keeps the status even if the event ends. Table General Purpose Input/Output (GPIO)-29 shows status registers for event detection.
  • Page 107 CXD5602 User Manual SCU_INT1 SCU_INT0 CRG_INT 0x04103444 PMU_WAKE_TRIG1 Reserved [31:2] Reserved INT_PMIC_I2CM Status of Event Detection 1: event is detected UNEXP_PMU 0: event is not detected 3.2.4.4.3 Clear of Event Detection Held statuses of Event Detection can be cleared by registers. If you write “1” on the register, clearing process will begin.
  • Page 108 CXD5602 User Manual INT_SYSIOPSUB [10] INT_GNSS PMU_RTCALMERR PMU_RTCALM2 PMU_RTCALM1 PMU_RTCALM0 SCU_INT3 SCU_INT2 SCU_INT1 SCU_INT0 CRG_INT 0x04103434 PMU_WAKE_TRIG1_CLR Reserved [31:2] Reserved INT_PMIC_I2CM The status can be cleared by writing UNEXP_PMU “1”. 3.2.4.4.4 Flow of Controlling Event Detection when used as Interrupt When you use the results of event detection as interrupts (refer to 3.2.4.4.1), for setting Event Detection and...
  • Page 109 CXD5602 User Manual interrupts INT_EN*, refer to 3.3.2 (Chapter of Interrupt). 1. Mask an interrupt. INT_EN0.EXDEVICE[0] = 0 2. Set the Event Detection (Pin Multiplexer, I/O pin selection, and way of detecting events). 3. Clear status register of Event Detection (to avoid errors caused by the result of the previous event detection).
  • Page 110 CXD5602 User Manual Figure General Purpose Input/Output (GPIO)-24 shows the timing diagram. (A) in the table means the time from when an external signal is asserted to when an event detection is held. The time depends on debounce setting. (B) means the time from when the clearing of event detection is executed to when the clearing is completed.
  • Page 111 CXD5602 User Manual RTC Clock Event Event Undetectable Event Detectable (from event detect to event detect clear done) Detectable External Signal Event detect (A)2~3 Cycle (B)7~8 Cycle Event detect latch Intterupt INT_IRQ0.* Intterupt mask INT_EN0.* Event detect clear PMU_WAKE_TRIG0_CLR.* PMU_WAKE_TRIG0_RAW 2.mask enable &...
  • Page 112 CXD5602 User Manual Interrupt 3.3.1 Overview and Features The LSI has individual interrupt controllers for the SYSIOP, GNSS, and APP. The 128 bit interrupt factors are connected to the CPUs of each SYSIOP, GNSS, and APP. Interrupt requests are divided into two main categories: one is internal interrupt generated from each CPU core or Peripheral, and another is external interrupt from I/O.
  • Page 113 CXD5602 User Manual Interrupt request from Wathdog Timer, WDTINT (bit[20]) is connected to IRQ of Processor 0, and reset signal from Watchdog Timer, WDTRES (bit[21]) is connected to Non-Maskable Interrupt (NMI) of Processor 0 (PID0 in Figure Interrupt-25). WDTRES (bit[23]) of GNSS and WDTRES (bit[23]) of APP are ORed with WDTINT(bit[20]), and the result is provided to NMI of Processor 0.
  • Page 114 CXD5602 User Manual [19:16] Interrupt request from SCU HOSTIFC [15:13] Interrupt request from Host I/F UART [12] Interrupt request from UART0 UARTDBG [11] Interrupt request from UART1 RTC_INT [10] ORed value between the following: - Interrupt request from RTC1_Misc - Interrupt request from RTC0_Misc...
  • Page 115 CXD5602 User Manual [30] Interrupt request from SPI Flash controller GNSSOR [29] ORed value of GNSS Receiver interrupts Reserved [28] Reserved CRYPTO_AES_MS [27:26] Interrupt request from Crypto (AES) BusMaster CRYPTO_AES_CO [25:24] Interrupt request from Crypto (AES) AES ADMAC [23:22] Interrupt request from ADMAC...
  • Page 116 The Power Management Unit (referred to as “PMU” hereinafter) is the block that performs overall power supply control of the CXD5602. The CXD5602 has a large power domain, which is divided into 11 domains. It performs ON control of necessary power domains only, while performing OFF control of the unnecessary ones, thereby reducing the power consumption.
  • Page 117 CXD5602 User Manual 3.4.1.1 Individual Power Supply Control within the Power Domains The SRAM or analog circuits such as the ADC within the power domains enable individual power supply control. -117/1010-...
  • Page 118 CXD5602 User Manual VDD_CORE PWD_PMU SRAM (Backup SRAM 32KB ) SRAM (Backup SRAM 32KB ) Always ON RCOSC XOSC SYSPLL PWD_SCU SRAM (FIFO 8 KB Sensor SRAM (FIFO 32 KB Domain SRAM (Sequencer RAM ) (HPADC (LPADC PWD_CORE SRAM (SYSIOP Tile...
  • Page 119 CXD5602 User Manual Using the PWD_APP of Figure PMU (Power Management Unit)-27 as an example, Figure PMU (Power Management Unit)-28 explains how individual power supply control is performed within the power domains. The PWD_APP has a total of 1.5 Mbytes of SRAM as main memory for the Application Processor. It comprises 12 logic tiles in 128 Kbyte units, and each one can control the power supply individually.
  • Page 120 Power supply states Description Power Off Both the CXD5602 (referred to as “the LSI” hereinafter) and the CXD5247 are OFF. Deep Sleep The LSI is OFF and the CXD5247 is ON. In this state, the RTC of the CXD5247 is counting, and time information can be obtained from the CXD5247 after the LSI is started.
  • Page 121 CXD5602 User Manual State: Power OFF CXD5247 CXD5602 System and Application GNSS Sensor State: Normal (Domain ON) IOP Domain Domain Domain Domain (PMIC) (Transition to each state is possible.) CXD5602 System and Application GNSS Sensor IOP Domain Domain ON Domain OFF...
  • Page 122 CXD5602 User Manual ADC (HPADC) ADC (LPADC) System and IOP PWD_CORE Domain SRAM (SYSIOP Tile #0 8 KByte) SRAM (SYSIOP Tile #0 8 KByte) SRAM (SYSIOP Tile #0 16 KByte) SRAM (SYSIOP Tile #0 32 KByte) SRAM (SYSIOP Tile #1 64 KByte)
  • Page 123 CXD5602 User Manual GNSS Domain PWD_GNSS_ITP PWD_GNSS SRAM (GNSS BB#0) SRAM (GNSS BB#1) SRAM (GNSS BB#2) SRAM (GNSS BB#3) SRAM (GNSS BB#4) SRAM (GNSS BB#5) RF (LNA) RF (MIX) RF (IF) RF (ADC) RF (LO) RF (PLL) 3.4.1.3 Block Diagram Figure PMU (Power Management Unit)-30 shows the block diagram of the PMU, which is mainly comprised of three blocks.
  • Page 124 CXD5602 User Manual layer and lower layer, the Power Control Sequencer first turns ON the power supply of the upper layer (PWD_APP) and then turns ON the power supply of the lower layer (PWD_APP_DSP). The CPU can recognize the completion of power supply control by the interrupt.
  • Page 125 Figure PMU (Power Management Unit)-31 PMU Clock System Reset The PMU is reset by full reset of the CXD5602 (external reset (RST_X) or RCOSC POR or WDT reset), by automatic release. Reset cannot be applied to the PMU alone. -125/1010-...
  • Page 126 CXD5602 User Manual 3.4.2 Register List Table PMU (Power Management Unit)-36 shows a list of registers related to each feature of the PMU. Table PMU (Power Management Unit)-36 PMU Register List Address Register Name Type Description Initial Value 0x04100000 PWD_CTL...
  • Page 127 CXD5602 User Manual 0x04100C40 GNSSDSP_RAMMODE_STAT Power supply status (SRAM for GNSS DSP) 0x0000FFFF 0x04103000 PSW_CHECK Power supply setting check 0x00000000 0x04103004 Reserved Reserved 0x04103034 0x04103C00 GNSS_RAMMODE_SEL Power supply setting (SRAM for GNSS) 0x00000000 0x04103C30 GNSS_RAMMODE_STAT Power supply status (SRAM for GNSS)
  • Page 128 CXD5602 User Manual 3.4.3 Register Descriptions 3.4.3.1 Register Settings Within the power supply control register (PWD_CTL, *_RAMMODE_SEL, ANA_PW_CTL), there is a Write Enable for each power supply. Power supply control is enabled only for power supplies with Write Enable set to “1”, allowing the control of the desired power supply without performing read-modify-write.
  • Page 129 CXD5602 User Manual Reserved [11] Reserved PWD_APP_SUB [10] Power supply control setting 1: ON, 0: OFF PWD_APP_DSP PWD_APP Reserved Reserved PWD_SYSIOP_SU Power supply control setting 1: ON, 0: OFF PWD_SYSIOP PWD_CORE Reserved [3:1] Reserved PWD_SCU Power supply control setting 1: ON, 0: OFF Note: The power supplies that are controlled are only the ones to which “1”...
  • Page 130 CXD5602 User Manual 3.4.3.3 Power Supply Control (SRAM) Table PMU (Power Management Unit)-39 and Table PMU (Power Management Unit)-40 show the registers related to power supply control of the SRAM. For the power supply control method, refer to the control flow described in Section 3.4.4.1.
  • Page 131 CXD5602 User Manual Reserved [7:6] Reserved SCUSEQ [5:4] 2'b00 Power supply control settings 2'b11: On mode SCU_FIFO1 [3:2] 2'b00 2'b01: Retention mode SCU_FIFO0 [1:0] 2'b00 2'b00: ShutDown mode 2'b10: Prohibited setting 0x0410001C HOSTIFC_RAM Reserved [31:4] Reserved MODE_SEL [25] Write Enable (SEQ)
  • Page 132 CXD5602 User Manual [24] Write Enable (RAM0) Reserved [23:12] Reserved RAM5 [11:10] 2'b00 Power supply control settings 2'b11: On mode RAM4 [9:8] 2'b00 2'b01: Retention mode RAM3 [7:6] 2'b00 2'b00: ShutDown mode RAM2 [5:4] 2'b00 2'b10: Prohibited setting RAM1 [3:2]...
  • Page 133 CXD5602 User Manual BKRAM0 [17:16] 2'b11 2'b11: On mode 2'b01: Retention mode 2'b00: ShutDown mode 2'b10: Prohibited setting Reserved [15:6] Reserved SCUSEQ [5:4] 2'b00 Power supply status SCU_FIFO1 [3:2] 2'b00 2'b11: On mode 2'b01: Retention mode SCU_FIFO0 [1:0] 2'b00 2'b00: ShutDown mode...
  • Page 134 CXD5602 User Manual RAM6 [1:0] 2'b00 3.4.3.4 Power Supply Control (Analog Circuit) Table PMU (Power Management Unit)-41 and Table PMU (Power Management Unit)-42 show the registers related to power supply control of the analog circuit. For the power supply control method, refer to the control flow described from Section 3.4.4.1.1 to Section 3.4.4.1.6.
  • Page 135 CXD5602 User Manual 0x04100008 ANA_EN_CTL Reserved [31:26] Reserved ON_XO_OSC_EN_ [25] XOSC oscillator Enable OFF_XO_OSC_EN [24] _CLR Reserved [23:21] Reserved ON_XO_OSCOUT [20] XOSC oscillator output Enable _EN_SET OFF_XO_OSCOU [19] T_EN_CLR ON_XO_EXT_EN_ [18] XOSC external clock operation Enable OFF_XO_EXT_EN [17] _CLR Reserved...
  • Page 136 CXD5602 User Manual RCOSC 3.4.3.5 Power Supply Control Request Table PMU (Power Management Unit)-43 shows the power supply control request registers. By writing “1” to PMU_PW_CTL.POWER_CTRL_ON, power supply control starts according to the value of the power supply control setting register (PWD_CTL, *_RAMMODE_SEL, ANA_PW_CTL).
  • Page 137 CXD5602 User Manual DONE Indicates the status after the interrupt factor is masked by the interrupt mask register. 0x04100044 PMU_RAW_INT Reserved [31:2] Reserved _STAT NOGO_CTRL Interrupt factor 1: Interrupt exists DONE 0: No interrupt 0x04100048 PMU_INT_CLR Reserved [31:2] Reserved The API may change the value. Perform read-modify-write when writing values to NOGO_CTRL and DONE.
  • Page 138 CXD5602 User Manual Table PMU (Power Management Unit)-46 Power Supply Setting Check Items PSW_CHECK Category Content checked ( ) [31] Power supply “RCOSC power supply and PMU clock source check” control When turning OFF the RCOSC, make sure to change the operation clock of the PMU from RCOSC to RTC_CLK_IN beforehand.
  • Page 139 CXD5602 User Manual [16] “Power supply setting check (RF and SRAM) of the GNSS Domain” When turning ON the SRAM for GNSS or RF, also turn ON the PWD_GNSS. When turning OFF the PWD_GNSS, also turn OFF the SRAM for GNSS and RF.
  • Page 140 CXD5602 User Manual When turning ON the SYSPLL, also turn ON the XOSC. When turning OFF the XOSC, also turn OFF the SYSPLL.  To turn ON the XOSC ON, SYSPLL: ANA_PW_CTL=0x00060006  To turn OFF the XOSC OFF, SYSPLL: ANA_PW_CTL=0x00060000 (...
  • Page 141 CXD5602 User Manual SRAM TOP_SCU_RAMMODE_SEL 0x00000200 0x0000020C 0x00000204 (FIFO 32 KByte) SRAM TOP_SCU_RAMMODE_SEL 0x00001000 0x00001030 0x00001010 (Sequencer RAM) - ADC (HPADC) ANA_PW_CTL 0x10000000 0x10001000 - ADC (LPADC) ANA_PW_CTL 0x20000000 0x20002000 - System PWD_CORE PWD_CTL 0x00100000 0x00100010 and IOP SRAM SYSCPU_RAMMODE_SEL...
  • Page 142 CXD5602 User Manual SRAM GNSSDSP_RAMMODE_SEL 0x40000000 0x40003000 0x40001000 (GNSS DSP Tile #6,7 128 KByte) SRAM (GNSS DSP Tile #8,9 GNSSDSP_RAMMODE_SEL 0x80000000 0x8000C000 0x80004000 128KByte) - PWD_SYSIOP_SUB PWD_CTL 0x00400000 0x00400040 - PWD_SYSIOP PWD_CTL 0x00200000 0x00200020 SRAM (HOSTIFC 1 KByte) HOSTIFC_RAMMODE_SEL 0x01000000...
  • Page 143 CXD5602 User Manual - GNSS PWD_GNSS_ITP PWD_CTL 0x10000000 0x10001000 - Domain PWD_GNSS PWD_CTL 0x20000000 0x20002000 SRAM (GNSS BB#0) GNSS_RAMMODE_SEL 0x01000000 0x01000003 0x01000001 SRAM (GNSS BB#1) GNSS_RAMMODE_SEL 0x02000000 0x0200000C 0x02000004 SRAM (GNSS BB#2) GNSS_RAMMODE_SEL 0x04000000 0x04000030 0x04000010 SRAM (GNSS BB#3) GNSS_RAMMODE_SEL...
  • Page 144 CXD5602 User Manual  GNSS_RAMMODE_SEL=0x3F000FFF (SRAM (GNSS BB#0-5) =ON) -144/1010-...
  • Page 145 CXD5602 User Manual 3.4.4.1.1 RCOSC OFF => ON Control Flow The following describes the flow to turn ON the power supply of the RCOSC. 1. RCOSC power supply ON setting ANA_PW_CTL=32'h00010001 2. Interrupt clear PMU_INT_CLR.CLR[1:0]=2'b11 3. Interrupt mask cancel PMU_INT_MASK.MSK[1:0]=2'b00 4.
  • Page 146 CXD5602 User Manual PMU_PW_CTL.POWER_CTRL_ON=1 5. Interrupt confirmation Confirm PMU_INT_STAT.STAT[1:0]=2'b01 6. Interrupt clear PMU_INT_CLR.CLR[1:0]=2'b11 3.4.4.1.2 XOSC OFF => ON Control Flow The following describes the flow to turn ON the power supply of the XOSC. 1. XOSC parameter setting Refer to Table PMU (Power Management Unit)-48 for the settings of ANA_EN_CTL.
  • Page 147 CXD5602 User Manual 3. The setting value of current adjustment is different for each frequency of the XOSC. Table PMU (Power Management Unit)-49 shows the assumed combination of the crystal oscillator, damping resistor, and the oscillation circuit setting. Table PMU (Power Management Unit)-49 Current Adjustment Setting...
  • Page 148 CXD5602 User Manual  XOSC_CTRL.IXO_LV_LOGICLK_EN=0 (for each function block) ON => OFF Control Flow The following describes the flow to turn OFF the power supply of the XOSC. As a precondition, make sure that the power supply of the SYSPLL is turned OFF during this operation.
  • Page 149 CXD5602 User Manual 3.4.4.1.3 SYSPLL OFF => ON Control Flow The following describes the flow to turn ON the power supply of the SYSPLL. As a precondition, perform the control with the power supply of the XOSC turned ON, and the clock supplied to the SYSPLL (XOSC_CTRL.IXO_LV_PLLCLK_EN=1).
  • Page 150 CXD5602 User Manual 6. Interrupt confirmation Confirm PMU_INT_STAT.STAT[1:0]=2'b01 7. Interrupt clear PMU_INT_CLR.CLR[1:0]=2'b11 8. Clock control Control the supply/stop of the clock in accordance with the function block or Analog circuit you use.  In the case of supplying the clock ...
  • Page 151 CXD5602 User Manual PMU_INT_CLR.CLR[1:0]=2'b11 4. Interrupt mask cancel PMU_INT_MASK.MSK[1:0]=2'b00 5. HPADC power supply ON control PMU_PW_CTL.POWER_CTRL_ON=1 6. Interrupt confirmation Confirm PMU_INT_STAT.STAT[1:0]=2'b01 7. Interrupt clear PMU_INT_CLR.CLR[1:0]=2'b11 8. Reset release SWRESET_SCU.XRST_SCU_HPADC=1 9. Clock control For details, refer to Section xxx. ON => OFF Control Flow The following describes the flow to turn OFF the power supply of the HPADC.
  • Page 152 CXD5602 User Manual 3.4.4.1.5 LPADC OFF => ON Control Flow The following describes the flow to turn ON the power supply of the LPADC. The PWD_SCU must be turned ON for this operation. 1. LPADC power supply ON setting ANA_PW_CTL=32'h20002000 2.
  • Page 153 CXD5602 User Manual 8. LPADC clock stop For details, refer to Section xxx. 3.4.4.1.6 OFF => ON Control Flow The following describes the flow to turn ON the power supply of the RF (LNA, MIX, IF, ADC, LO, PLL). The XOSC, PWD_GNSS_ITP, and PWD_GNSS must be turned ON for this operation.
  • Page 154 CXD5602 User Manual 3.4.5 Power Supply Control Example 3.4.5.1 Actual Example of Power Supply Control By ORing the power supply control setting (PWD_CTL, *_RAMMODE_SEL, ANA_PW_CTL) of each power supply, you can control multiple power supplies together by a single power supply control request (PMU_PW_CTL.POWER_CTRL_ON).
  • Page 155 3.4.5.2 Application Processor Sleep/Wakeup Control In this document, the term Sleep refers to cases when any of the power domains of the CXD5602 turn OFF, or when the DSP belonging to that power domain is not operating. On the other hand, Wakeup refers to cases when they turn ON, or when the DSP belonging to that power domain starts operating.
  • Page 156 CXD5602 User Manual PMU (Power Management Unit)-32 shows the control flow diagram. Control Overview  Sleep control The Application Processor requests Sleep (PWD_APP_DSP "OFF”) control to the System and I/O Processor. After the Application Processor has made this request, it enters WFI state. The System and I/O Processor then confirms that the Application Processor has entered WFI state, and performs OFF control of the PWD_APP_DSP.
  • Page 157 CXD5602 User Manual 3. Turn ON the PWD_APP_DSP (Refer to Section 3.4.4.1 Basic flow of power supply control)  Control of Application Processor side (reference) Starts when the System and I/O Processor turns ON the power supply of the PWD_APP_DSP 1.
  • Page 158 3.5.1 Overview The Clock Reset Generator (CRG) is the block that controls the clock and reset of the overall CXD5602. For the clock sources, there are XOSC and RCOSC, SYSPLL, RTC Clock, and RF. The RTC Clock is supplied from the outside of the CXD5602.
  • Page 159 CXD5602 User Manual Application Domain 163MHz(High performance mode) Divider / 40MHz(Low Power mode) Application Divider Processor APP Bus Divider Divider Peripheral CIS I/F 49.104MHz Divider SDIO 2D Graphics 49.104MHz eMMC Divider Divider AUDIO MCLK 24.576kHz System and IOP Domain 100MHz(High performance mode)
  • Page 160 CXD5602 User Manual 3.5.3 Analog Circuits The CRG has three analog circuits (RCOSC block, XOSC block, and SYSPLL block). The following shows the setting confirmation registers of each analog circuit. Some of them are RW registers, but use them as RO registers.
  • Page 161 CXD5602 User Manual *Supported frequencies: 26 MHz The XOSC can be used as the processor’s operation clock and is also supplied as the reference clock to the SYSPLL and RF. 3.5.3.2.1 Register Descriptions Table Clock and Reset (Clock Reset Generator)-52 shows the control registers related to the XOSC block.
  • Page 162 CXD5602 User Manual 3.5.3.3 SYSPLL Block Setting Confirmation The frequencies of SYSPLL can be confirmed by the XOSC frequency and division ratio setting register as shown in Table Clock and Reset (Clock Reset Generator)-53. Table Clock and Reset (Clock Reset Generator)-53 SYSPLL Frequency Confirmation XOSC SYS_PLL_CTRL2.ISP_L...
  • Page 163 CXD5602 User Manual _CTRL2 ISP_LV_SELFBDIV [29:27] 3'b001 FBDIV frequency division ratio switching Reserved [26:0] Reserved 3.5.4 Clock Setting Confirmation 3.5.4.1 Register Descriptions The following describes the status confirmation registers of the clock switching and the clock Enable. Some of them are RW registers, but use them as RO registers.
  • Page 164 CXD5602 User Manual Figure Clock and RORTC_STAT_CLK [13] Indicated as SEL(3) in Reset (Clock Reset Generator)-34 _SEL2 Clock source switching status for power supply control 0: RCOSC 1: RTC Clock Reserved [12] Reserved Figure Clock and RFPLL1_STAT_CLK [11:10] Indicated as SEL(2) in...
  • Page 165 CXD5602 User Manual 3.5.4.1.2 Clock Enable Table Clock and Reset (Clock Reset Generator)-56 shows the status registers of clock Enable (clock supplied/clock stopped). Table Clock and Reset (Clock Reset Generator)-56 Clock Enable Status Registers Address Register Bit Field Type Initial...
  • Page 166 CXD5602 User Manual 3.5.5 Power Domain Reset The reset of each power domain can be controlled by the registers excluding some domains. When releasing a reset, first perform ON control of the corresponding power domain, and then release the reset.
  • Page 167 By detecting the asserting of the WDT within the System and I/O Processor, a reset is automatically issued to each block of the CXD5602. However, reset by the WDT is not performed for the following registers or SRAM. (Reset is performed only during POR).
  • Page 168 CXD5602 User Manual  Register: RAMMODE.LS (0x041006E4)  Register: BOOT_CAUSE.RAW_WDT_REBOOT (0x04100484)  SRAM: BackUpRAM Note: In the case of accessing the BackUpRAM after reset by WDT, clear the WDT factor register. The WDT asserting flag of the System and I/O Processor is stored in the BOOT_CAUSE.RAW_WDT_REBOOT.
  • Page 169 CXD5602 User Manual RAW_INITIAL_BO Boot flag 1: Boot by POR or WDT When booted by POR RAW_WDT_REBOOT =0 RAW_INITIAL.BOOT =1 When booted from WDT RAW_WDT_REBOOT =1 RAW_INITIAL.BOOT =1 -169/1010-...
  • Page 170  RTC1 (power supply domain: PWD_SYSIOP) RTC0 is supplied with VDD_CORE of CXD5602, and after the reset release, it continues counting time. On the other hand, RTC1 counts time only when PWD_SYSIOP is powered on. When the PWD_SYSIOP power supply is turned off, the Time Counter returns to “0”.
  • Page 171 The clock source of the RTC is selected from either a real time clock (32.768 kHz) provided by an RTC IC outside CXD5602 or real time clock from an internal clock (about 32 kHz) divided from the RCOSC. Initial value after the reset release is “0”...
  • Page 172 Alarm Timers. Registers are set via APB IF block. APB IF block is operated by PWD_SYSIOP power supply. RTC0 can select one Alarm from three Alarms, and output it from CXD5602 RTC_IRQ_OUT terminal. Update function of Time Counter (Time Update) is shown in the block diagram on the next page.
  • Page 173  How to set Time Synchronization 3. You can set another RTC Time Counter value inside CXD5602. 4. At the timing of asserting either External Alarm Flag (Interrupt from PMIC_INT) or Alarm from RTC inside CXD5602 (RTCx_ExtAlm), you can set the designated Time Counter value.
  • Page 174 CXD5602 User Manual to Other RTC Counter Time Counter {Post, Pre} from Other RTC Counter APB IF WrRegPostCnt WrRegPreCnt OffsetVal 1:Register WrRegReq 2:Offset Time Counter Update OffsetReq update done 3:RTC Sync Flag RtcSyncReq 4:External Sync WrIntCtrl CntUpdateEn WrIntCtrl.Edge RTC0_ExtAlm RTC1_ExtAlm...
  • Page 175 CXD5602 User Manual 3.6.5 Detailed Function and Control Specification 3.6.5.1 List of Registers Table RTC-63 Register List of Counter Value Write Control System Offset Register Name Attribute Function Initial Value 0x00 WrRegPostCnt Time Counter value (PostCounter) 0x00000000 0x04 WrRegPreCnt Time Counter value (PreCounter)
  • Page 176 CXD5602 User Manual Table RTC-65 Register List of Alarm Control System Offset Register name Attribute Function Initial Value 0x50 SetAlmPostCnt0 Comparison Value of PostCounter for Alarm0 0xFFFFFFFF 0x54 SetAlmPreCnt0 Comparison Value of PostCounter for Alarm0 and Status 0x00007FFF The status of some bits is RO.
  • Page 177 CXD5602 User Manual (Comparison Value of PostCounter for Alarm1 currently used by RTC) 0x9C DbgSetAlmPreCnt1 Read Value of DbgSetAlmCnt1[14:0] 0x00007FFF (Comparison Value of PreCounter for Alarm1 currently used by RTC) 0xA0 DbgSetAlmPostCnt2 Read Value of DbgSetAlmCnt2[46:15] 0xFFFFFFFF (Comparison Value of PostCounter for Alarm2 currently...
  • Page 178 CXD5602 User Manual 3.6.5.2 Register Descriptions By turning off the PWD_SYSIOP power supply, all register values of RTC1 (from 0x04109000 to 0x041090C8) return to initial values. However, no register values of RTC0 (from 0x04108000 to 0x041080C8) return to initial values. When tuning on the PWD_SYSIOP power supply again, alarm information set in the RTC0 can be read.
  • Page 179 CXD5602 User Manual 3.6.5.2.2 WrRegPreCnt(0x04) Reserved Rese rved  bit[14:0] : Pre[14:0] (PreCounter Write Value) This is a value reflected on PreCounter of RTC when Write Request (WrRegReq) is issued, or when RTC receives External Alarm Flag. 3.6.5.2.3 WrRegReq(0x08) Reserved...
  • Page 180 CXD5602 User Manual When WrReg(Post/Pre)Cnt value is reflected to (Post/Pre)Counter and Write Request becomes possible to be issued again, this register is cleared to “0” automatically. 3.6.5.2.4 WrIntCtrl(0x18) Reserved Reserved Edge Reserved Busy  bit[0] : Busy (Request for waiting for External Alarm Flag) When you write “1”...
  • Page 181 CXD5602 User Manual 3.6.5.2.5 WrIntClr(0x1C) Reserved Reserved Busy  bit[0] : Busy (Cancel of waiting for External Alarm Flag) When you write “1” on Busy, this register cancels Request for waiting for External Alarm Flag (WrIntCtrl.Busy is cleared to “0”).
  • Page 182 CXD5602 User Manual 3.6.5.2.7 OffsetReq(0x24) Reserved Busy Reserved  bit[0] : BusyA (Correction request for RTC Counter value) This register issues a correction request for RTC Counter value. After issuing the request, it adds OffsetVal value to RTC Counter. BusyA Description of Functions Writing 0: You cannot write “0”.
  • Page 183 CXD5602 User Manual 3.6.5.2.8 RtcSyncReq(0x28) Reserved Reserved  bit[0] : Req (Synchronization request with other RTC Counter) When you write “1”, this register issues a synchronization request. After issuing the request, this register makes one RTC import the other internal RTC counter value to its own value, and makes it synchronize with the other RTC.
  • Page 184 CXD5602 User Manual 3.6.5.2.9 RdReq(0x30) Reserved Busy Reserved  bit[0] : BusyA (Read Request) When you write “1”, this register issues a Read Request. Once the Read Request is issued, RTC Counter value at the time when it is issued can be read from RdPostCnt and RdPreCnt.
  • Page 185 CXD5602 User Manual 3.6.5.2.11 RdPreCnt(0x38) Reserved Rese rved  bit[14:0] : Pre[14:0] (PreCounter value at the time of Read Request) By reading this register, you can see the PreCounter value at the point of time when the read request was issued.
  • Page 186 CXD5602 User Manual 3.6.5.2.12 RtPostCnt(0x40) Post Post  bit[31:0] : Post[31:0] (PostCounter value when RtPostCnt was read) The following are differences from Rd(Post/Pre)Cnt.  There is no need to issue a Read Request (RdReq).  After you write “1” on RdReq, there is no restriction to wait for RdReq to become 0.
  • Page 187 CXD5602 User Manual 3.6.5.2.14 SetAlmPostCnt0(0x50) Post Post  bit[31:0] : Post[31:0] (Comparison Value of PostCounter for AlmFlg.Flg0 and AlmFlg.ErrFlg0) This register sets Operation time (PostCounter) of Alarm0. This register compares SetAlm(Post/Pre)Cnt0 with RTC Counter (PostCounter and PreCounter) by using absolute value, and generates Normal Alarm0 or Error Alarm0.
  • Page 188 CXD5602 User Manual  3.6.5.2.15 SetAlmPreCnt0(0x54) Reserved Busy Rese rved  bit[14:0] : Pre[14:0] (Comparison value of PreCounter for AlmFlg.Flg0 and AlmFlg.ErrFlg0) This register sets operation time (PreCounter) of Alarm0. It takes time to reflect a new Alarm Operation time. During reflecting, do not update the Alarm Operation time.
  • Page 189 CXD5602 User Manual 3.6.5.2.16 SetAlmPostCnt1(0x58) Post Post  bit[31:0] : Post[31:0] (Comparison Value of PostCounter for AlmFlg.Flg1 and AlmFlg.ErrFlg1) This register sets Operation time (PostCounter) of Alarm1. This register compares SetAlm(Post/Pre)Cnt1 with RTC Counter (PostCounter and PreCounter) by using absolute value, and generates Normal Alarm1 or Error Alarm1.
  • Page 190 CXD5602 User Manual Reading 1: Alarm Operation time is being reflected. SetAlm(Post/Pre)Cnt1 must not be written. 3.6.5.2.18 SetAlmPostCnt2(0x60) Post Post  bit[31:0] : Post[31:0] (Comparison Value of PostCounter for AlmFlg.Flg2) This register sets Operation time (PostCounter) of Alarm2. The function of Alarm2 is different from that of Alarm0 and Alarm1.
  • Page 191 CXD5602 User Manual SetAlm(Post/Pre)Cnt2 must not be updated). Once the reflection is completed, Busy becomes “0” automatically. Busy Description of Functions Reading 0: Alarm Operation time is not set or reflected completely. Reading 1: Alarm Operation time is being reflected. SetAlm(Post/Pre)Cnt2 must not be written.
  • Page 192 CXD5602 User Manual Writing 0: invalid Writing 1: deasserts Normal Alarm Flag2 When Normal Alarm Flag2 is deasserted, this register is cleared to “0” automatically.  bit[16] : ErrFlg0 (Clear of Error Alarm Flag0) When you write “1” on AlmClr.Flg0, Error Alarm0 Interrupt is deasserted, and Error Alarm Flag0 is cleared.
  • Page 193 CXD5602 User Manual If conditions are met, interrupt will be asserted. 1'b0 is set on En, an interrupt request is disabled. However, status register AlmFlg.Flg0 transitions to 1'b1 if conditions are met.  bit[8] : Busy (Write Busy Status) This register indicates how far AlmOutEn0 register is reflected.
  • Page 194 CXD5602 User Manual 3.6.5.2.22 AlmOutEn1(0x78) Reserved Reserved Busy Reserved  bit[0] : En (Enable Signal for Normal Alarm1 Interrupt) This register does the settings for notifying processor of Normal Alarm Flag1. It takes time to reflect the settings. During reflecting, do not update the settings. You can check whether it is in the process of reflecting by using Busy.
  • Page 195 CXD5602 User Manual ErrEn Description of Functions Writing 0: disables an interrupt request to processor. Even if conditions are met, interrupt will be deasserted. Writing 1: enables an interrupt request to processor. If conditions are met, interrupt will be asserted.
  • Page 196 CXD5602 User Manual 3.6.5.2.23 AlmOutEn2(0x7C) Reserved Reserved Busy Reserved  bit[0] : En (Enable Signal for Normal Alarm2 Interrupt) This register does the settings for notifying processor of Normal Alarm Flag2. It takes time to reflect the settings. During reflecting, do not update the settings. You can check whether it is in the process of reflecting by using Busy.
  • Page 197 CXD5602 User Manual 3.6.5.2.24 AlmFlg(0x80) Reserved Flg1 Flg0 Reserved Flg2 Flg1 Flg0 By reading this register, you can see Normal Alarm and Error Alarm Flag (Alarm Interrupt value before controlling registers Enabled or Disabled by using AlmOutEn). When the conditions are as described in the Table RTC-68 below, an Alarm occurs.
  • Page 198 CXD5602 User Manual Normal Alarm1 Interrupt is asserted.  bit[2] : Flg2 (Normal Alarm Flag2) Flg2 Description of Functions Normal Alarm2 Interrupt is deasserted. Normal Alarm2 Interrupt is asserted.  bit[0] : ErrFlg0 (Error Alarm Flag0) Flg0 Description of Functions Error Alarm0 Interrupt is deasserted.
  • Page 199 CXD5602 User Manual Rese rved  bit[14:0] : Dbg[14:0] (Current SetAlmPreCnt0 value) This register is used for debugging. By reading this register, you can see SetAlmPreCnt0 Value that is currently used in RTC. By using this register, you can check whether the set value has been normally reflected on SetAlmPreCnt0 or not.
  • Page 200 CXD5602 User Manual currently used in RTC. By using this register, you can check whether the set value has been normally reflected on SetAlmPreCnt1 or not. 3.6.5.2.29 DbgSetAlmPostCnt2(0xA0)  bit[31:0] : Dbg[31:0] (Current SetAlmPostCnt2 value) This register is used for debugging. By reading this register, you can see comparison value of PostCounter for Alarm2 that is currently used in RTC.
  • Page 201 CXD5602 User Manual 3.6.5.2.31 CntUpdateClr(0xB0) Reserved Reserved When RTC Counter has been updated completely, the interrupt flag notifying that RTC Counter has been updated is asserted (set). If Clear Register is written, the interrupt flag can be deasserted (reset) instantly.
  • Page 202 CXD5602 User Manual 3.6.5.2.33 CntUpdateFlg(0xB8) Reserved Reserved By reading this register, you can see the interrupt flag notifying that RTC Counter has been updated (Interrupt value before being controlled Enabled or Disabled by CntUpdateEn). If RTC Counter is updated under the following conditions, CntUpdateFlg becomes “1”.
  • Page 203 CXD5602 User Manual 3.6.5.2.34 DiffSignBit(0xC0) Reserved Reserved  bit[0] : Val (sign bit of difference value from other RTC Counter) By reading this register, you can see sign when difference (means one RTC Counter (47 bits) minus other RTC Counter (47 bits)) is calculated.
  • Page 204 CXD5602 User Manual 3.6.5.2.36 DiffPreCnt (0xC8) Reserved Rese rved  bit[14:0] : Val[14:0] (Difference from other RTC Counter value) By reading this register, you can see lower 15 bits of the difference (47 bits) (means one RTC Counter (47 bits) minus other RTC Counter (47 bits)).
  • Page 205 CXD5602 User Manual EXTALM_SEL Description of Functions 1 is output as an External Output Alarm (RTC0_ExtAlm). (When EXTALM_POL indicates “1”)  bit[4] : EXTALM_POL (External Alarm Output Select Signal) This register sets signal logic (positive logic or negative logic) of External Output Alarm.
  • Page 206 CXD5602 User Manual 3.6.5.2.38 RTC1_RTC_CTL (0x04100730) Reserved EXTALM_S Reserved Reserved SYNC_SEL Reserved Reserved  bit[1:0] : EXTALM_SEL [1:0] (External Alarm Output Select Signal) This register selects one AlarmFlag from AlarmFlag0, AlarmFlag1, and AlarmFlag2 as an Alarm output outside (RTC1_ExtAlm). EXTALM_SEL Description of Functions AlarmFlag0 is used as an External Output Alarm (RTC1_ExtAlm).
  • Page 207 CXD5602 User Manual EXTALM_SEL Description of Functions RTC1_ExtAlm is used as a trigger of Time Synchronization. This alarm is used when IOCSYS_IOMD0.PMIC_INT indicates 2. For details, refer to Chapter 3.1.4.3.2. This alarm is used when IOCSYS_IOMD0.PMIC_INT indicates 3. For details, refer to Chapter 3.1.4.3.3.
  • Page 208 CXD5602 User Manual 3.6.5.3 Control Flow 3.6.5.3.1 Update of RTC Counter Value This function is used when you reflect values, which are set by registers, on RTC Counter value (PostCounter[31:0], PreCounter[14:0]). The sequence is as follows. 1. On WrRegPostCnt register, write a value that you want to reflect on PostCounter.
  • Page 209 CXD5602 User Manual 3.6.5.3.3 Synchronization of External RTC Synchronization of External RTC is a function that sets time of RTC inside CXD5602 by receiving interrupts from outside including PMIC (PMIC_INT). Synchronizing CXD5602 with CXD5247 The sequence when CXD5602 (hereinafter called the LSI) is synchronized with CXD5247 (hereinafter called the PMIC) is described below.
  • Page 210 4. Write “1” on WrIntCtrl.Busy register. Receiving PMIC External Alarm from PMIC_INT, synchronization between RTC in the PMIC and RTC in the CXD5602 will be completed on the time (Y[46:6]-1) designated in 2 above. Once synchronization has been completed, WrIntCtrl.Busy becomes “0”.
  • Page 211 Difference Calculation between CXD5602 and CXD5247 RTC of CXD5602 operates at 32.7 kHz clock frequency. Meanwhile, RTC of CXD5247 operates at 512 Hz clock frequency. For this reason, there might be time difference between the PMIC and the LSI when CXD5247 (hereinafter called PMIC) is synchronized with CXD5602 (hereinafter called LSI).
  • Page 212 CXD5602 User Manual 3. On SetAlmPostCnt0 register, write the time that you want to output an Alarm. Make sure to write SetAlmPostCnt0 before SetAlmPreCnt0. 4. On SetAlmPreCnt0 register, write the time that you want to output an Alarm. An Alarm is output at the time set in 3 and 4 above.
  • Page 213 CXD5602 User Manual Table I2C-70 XOSC (26 MHz), High Performance Mode Clock source SYSPLL XOSC RCOSC frequency M Hz 195.000 156.000 26.000 8.192 0.032768 SYSIOP (ck_ahb_gear,ck_com_gear) M Hz 48.750 39.000 26.000 8.192 0.032768 I2C2 BCK kbps 1.424696 I2C4 BCK kbps 1.424696...
  • Page 214 CXD5602 User Manual 3.7.2.1 Register List Table I2C-80 shows a register list of the I2C0 and I2C1. Table I2C-72 I2C0 and I2C1 Register List Address Register Name Type Description initial Value 0x0418D400 I2C0 register (For details, refer to the API)
  • Page 215 CXD5602 User Manual 3.7.2.3 Clock Supply Start and Stop 3.7.2.3.1 Clock Supply Start The following describes the method to start clock supply to the I2C0 and I2C1. 1. Clock supply start (internal circuit initialization) SCU_CKEN.SCU_I2C0 = 1'b1 SCU_CKEN.SCU_I2C1 = 1'b1...
  • Page 216 CXD5602 User Manual 3.7.3 I2C2 The I2C2 is the I2C master and supports Standard and Fast Mode. 3.7.3.1 Register List Table I2C-81 shows a register list of the I2C2. Table I2C-73 I2C2 Register List Address Register Name Type Description initial...
  • Page 217 CXD5602 User Manual 3.7.3.3 Clock Supply Start and Stop 3.7.3.3.1 Clock Supply Start The following describes the method to start clock supply to the I2C2. 1. Clock supply start of the AHB/APB Bus Bridge. SYSIOP_SUB_CKEN.COM_BRG = 1'b1 SYSIOP_SUB_CKEN.AHB_BRG_COMIF = 1'b1 2.
  • Page 218 CXD5602 User Manual 3.7.4 I2C4 The I2C4 is the I2C master and supports Standard and Fast Mode. 3.7.4.1 Register List TTable I2C-82 shows a register list of the I2C4. Table I2C-74 I2C4 Register List Address Register Name Type Description initial...
  • Page 219 CXD5602 User Manual 3.7.4.3 Clock Supply Start and Stop 3.7.4.3.1 Clock Supply Start The following describes the method to start clock supply to the I2C4. 1. Clock supply start (internal circuit initialization). PMU_CORE_CKEN.RTC_PCLK = 1'b1 PMU_CORE_CKEN.PMU_RTC_PCLK = 1'b1 Reads the address 0x04106000 of I2C4 (dummy read to wait for completion of preceding setting) 2.
  • Page 220 CXD5602 User Manual DMAC 3.8.1 Overview and Features List of DMACs  SDMAC (Power domain: PWD_SYSIOP) The SDMAC is for the Sensor and performs DMA transfer between the SCU and each SRAM  HDMAC (Power domain: PWD_SYSIOP) The HDMAC is for the HOSTIFC and performs DMA transfer between the HOSTIFC and each SRAM ...
  • Page 221 CXD5602 User Manual Table DMAC-83 shows the DMA request bit assignment for Memory-to-peripheral transfer and Peripheral-to-memory transfer of each DMAC. The ADMAC supports Memory-to-memory transfer only. Table DMAC-75 DMA Request Bit Assignment Request Bit SDMAC HDMAC SYDMAC SYSUBDMAC ADMAC IDMAC...
  • Page 222 CXD5602 User Manual 3.8.3 SDMAC ® Adds a feature to notify the CPU of independent interrupts or each DMA channel to the PrimeCell µDMA Controller (PL230).  The interrupt signal is changed from pulse to level  The interrupt factor register (dma_done, dma_err) is added.
  • Page 223 CXD5602 User Manual 3.8.3.1 Register List Table DMAC-84 shows the registers that control the SDMAC. Table DMAC-76 SDMAC Control Register List Address Register Name Type Description initial Value ® 0x04120000 PrimeCell µDMA Controller (PL230) register 0x0412004C 0x04120050 dma_done Notifies DMA transfer completion of each DMA channel...
  • Page 224 CXD5602 User Manual 3.8.3.2 Register Descriptions Table DMAC-85 shows descriptions of the registers added to the SDMAC. Table DMAC-77 SDMAC Added Registers Bit Field Initial Address Register Name Type Description Name Value 0x04120050 dma_done dma_done [31:0] DMA channel number of DMA transfer completion...
  • Page 225 CXD5602 User Manual 3.8.3.4 Clock Supply Start and Stop 3.8.3.4.1 Clock Supply Start Perform the following control to start supplying the HCLK clock of the SDMAC. 1. Reset release Automatically released when the PWD_SYSIOP power domain is turned ON. 2. Clock supply start SYSIOP_CKEN.AHB_DMAC0=1'b1...
  • Page 226 CXD5602 User Manual 3.8.4.1 Register List Table DMAC-86 shows the registers that control the HDMAC. Table DMAC-78 HDMAC Control Register List Address Register Name Type Description initial Value ® 0x04121000 PrimeCell Single Master DMA Controller (PL081) register 0x04121FFC 3.8.4.2 Clock and Reset Figure DMAC-45 shows the clock and reset system diagram of the HDMAC.
  • Page 227 CXD5602 User Manual 3.8.4.3.2 Clock Supply Stop Perform the following control to stop supplying the HCLK clock of the HDMAC. 1. Clock supply stop SYSIOP_CKEN.AHB_DMAC1=1'b0 3.8.5 SYDMAC 3.8.5.1 Register List Table DMAC-87 shows the registers that control the SYDMAC. Table DMAC-79 SYDMAC Control Register List...
  • Page 228 CXD5602 User Manual 3.8.5.3 Clock Supply Start and Stop 3.8.5.3.1 Clock Supply Start Perform the following control to start supplying the HCLK clock of the SYDMAC. 1. Reset release Automatically released when the PWD_SYSIOP power domain is turned ON. 2. Clock supply start SYSIOP_CKEN.AHB_DMAC2=1'b1...
  • Page 229 CXD5602 User Manual RCOSC ck_cpu_bus SYSUBDMAC ck_rf_pll_1 ck_ahb_gear RTC_CLK_IN XOSC HCLK (32.768kHz) GATE Auto(PWD_SYSIOP_SUB Power Domain ON) SYSPLL HRESETn PWD_RESET0.PWD_SYSIOP_SUB CKSEL_ROOT.CPU_PLL_DIV5 CKSEL_ROOT.RFPLL1_STAT_CLK_SEL4 CKSEL_ROOT.STAT_CLK_SEL4 CKDIV_CPU_DSP_BUS.CK_M0 CKDIV_CPU_DSP_BUS.CK_AHB SYSIOP_SUB_CKEN.AHB_DMAC3 Figure DMAC-47 SYSUBDMAC Clock and Reset System 3.8.6.3 Clock Supply Start and Stop 3.8.6.3.1 Clock Supply Start Perform the following control to start supplying the HCLK clock of the SYSUBDMAC.
  • Page 230 CXD5602 User Manual 3.8.7.2 Clock and Reset Figure DMAC-48 shows the clock and reset system diagram of the ADMAC. RCOSC CK_APP XOSC RTC_CLK_IN(32.768kHz) GATE GEAR_AHB.gear_m_ahb SYSPLL GEAR_AHB.gear_n_ahb ADMAC CK_GATE_AHB.ck_gate_dmac GATE HCLK RESET.xrs_dsp_gen HRESETn APP_CKSEL.APP_PLL_DIV5 APP_CKSEL.STAT_SP_CLK_SEL4 IDMAC APP_CKSEL.STAT_APP_CLK_SEL4 CK_GATE_AHB.ck_gate_img GATE HCLK APP_CKEN.APP...
  • Page 231 CXD5602 User Manual 3.8.8 IDMAC ® The functions of the IDMAC have been modified based on the PrimeCell DMA Controller (PL080) from ARM Limited. Features of the IDMAC  There are five DMA channels, each of which supports unidirectional transfer.
  • Page 232 CXD5602 User Manual 3.8.8.1 Register List Table DMAC-8 shows the registers that control the IDMAC. Table DMAC-8 IDMAC Control Register List Address Register Name Type Description initial Value 0x04123000 DMACIntStatus Interrupt Status Register 0x04123004 DMACIntTCStatus Interrupt Terminal Count Status Register...
  • Page 233 CXD5602 User Manual 0x04123504 DMACITOP1 Integration Test Output Register 1 0x04123508 DMACITOP2 Integration Test Output Register 2 0x0412350C DMACITOP3 Integration Test Output Register 3 0x04123510 Reserved Reserved 0x041237FC 0x04123800 DMACAUX0 DMAC Auxury Register 0 0x04123804 DMACAUX1 DMAC Auxury Register 1...
  • Page 234 CXD5602 User Manual [13] 1'b0 When the arbiter within the DMAC schedules the transfers (for multiple transfer requests), scheme that determines the priority can be read out. Takes the following values depending on the configuration of the DMAC. 0: Fixed-priority...
  • Page 235 CXD5602 User Manual DMACSR [15:0] Masks the input of the DMA data transfer EQMASK request input terminal DMASREQ[15:0]. When masked, only DMABREQ[15:0] becomes valid. 0: DMASREQ input is masked 1: DMASREQ input is valid Note that the setting of this register...
  • Page 236 CXD5602 User Manual Channel Control [28] 1'b0 When DMACConfiguration.TS=1 register mapping changes (TransferSize expanded mapping) according to the TS value Indicates the AHB master channel used for the destination data transfer. DMACConfiguration 0: Selects AHB master 1 for the register.
  • Page 237 CXD5602 User Manual DSIZE [22:21] When DMACConfiguration.TS=1 (TransferSize expanded mapping) Indicates the burst size of the destination data transfer. Make sure to set this value to the burst size of the destination peripheral or to the memory boundary size if the memory is the destination.
  • Page 238 CXD5602 User Manual TRANSFE [18:0] When DMACConfiguration.TS=1 RSIZE (TransferSize expanded mapping) When the DMA controller is the flow controller, the amount of data transfer to be performed is written to this register. Values can be written from 0 to 524287.
  • Page 239 CXD5602 User Manual DESTME [25] Sets access of the AHB port, which is set MBURST as the memory access of the Destination side, so that it always conforms to the burst length set by DBSize. This is used to raise the efficiency of memory access.
  • Page 240 CXD5602 User Manual 0x04123114 DMACDefLLI_n DEFLLI [31:2] The address that points to the Default (n=0-3,step=0x20) Linked List Item. When transfer starts with the DefLLI function enabled, the LLI The register for setting of the address that DefLLI points to is the DefLLI.
  • Page 241 CXD5602 User Manual Important Points to Note  About locked transfer Locked transfer is not supported. Do not set the corresponding function registers.  DMACConfiguration Make sure to set the M1, M2 bits to little endian. Setting them to big endian is prohibited.
  • Page 242 CXD5602 User Manual 3.8.8.3 Clock and Reset Figure DMAC-50 shows the clock and reset system diagram of the IDMAC. RCOSC CK_APP XOSC GATE RTC_CLK_IN(32.768kHz) GEAR_AHB.gear_m_ahb SYSPLL GEAR_AHB.gear_n_ahb ADMAC CK_GATE_AHB.ck_gate_dmac GATE HCLK RESET.xrs_dsp_gen HRESETn APP_CKSEL.APP_PLL_DIV5 APP_CKSEL.STAT_SP_CLK_SEL4 IDMAC GATE APP_CKSEL.STAT_APP_CLK_SEL4 CK_GATE_AHB.ck_gate_img HCLK APP_CKEN.APP...
  • Page 243 CXD5602 User Manual SCU (Sensor Control Unit) 3.9.1 SCU Overview and Features The Sensor Control Unit (referred to as “SCU” hereinafter) is the block that provides control of capturing output data from the external sensor information. It offers the following features.
  • Page 244 CXD5602 User Manual  Random Access Partitions x 1 Each partition is assigned to regions divided within an SRAM having 40 KByte (32bit x 2048words + 32bit x 8192 words) space. Power supply control of the FIFO SRAM can be performed from the PMU (Power Supply Control Unit) outside the SCU.
  • Page 245 CXD5602 User Manual 3.9.2 SCU Block Diagram CXD5602 ASYNC ASYNC PWD_SCU SCU_LOGIC SCU_REG HOSTIFC SEQUENCER MATH_PROC Arbiter Arbiter I2C0 I2C1 ADCIF SCU_FIFO HPADC LPADC SCU_ANALOG Figure SCU (Sensor Control Unit)-51 Block Function Overview -245/1010-...
  • Page 246 CXD5602 User Manual 3.9.3 Memory Map Figure SCU (Sensor Control Unit)-52 shows the MemoryMap as seen from the SYSCPU. 0x003F_FFFF Reserved 0xFFFF_FFFF 0x001A_CFFF UART(4K) Reserved 0x001A_C000 (1792M) 0x001A_BFFF 0x9000_0000 SPIM(4K) 0x001A_B000 0x8FFF_FFFF 0x001A_AFFF SPIFLASHIF I2CM(4K) 0x001A_A000 (256M) 0x001A_9FFF 0x8000_0000 HostUART(4K)
  • Page 247 CXD5602 User Manual Figure SCU (Sensor Control Unit)-53 Memory Mapping within the SCU as seen from the Upper CPUs The Reserved area within this Figure is writing-invalid (no error response) and “0” read during readout (no error response). The data storage region including the FIFO RAM (32 KByte) and FIFO RAM (8 KByte) is 40 KByte. Refer to Section 3.9.8 for details.
  • Page 248 CXD5602 User Manual The Reserved area within this Figure is writing-invalid (no error response) and “0” read during readout (no error response). Figure SCU (Sensor Control Unit)-54 Memory Mapping as seen from the Internal Sequencer Figure SCU (Sensor Control Unit)-55 shows the Memory Mapping as seen from the SCU window of the HOSTIFC.
  • Page 249 CXD5602 User Manual 3.9.4 Clock Control 3.9.4.1 Clock Summary Table SCU (Sensor Control Unit)-82 Clock Summary Clock Name Maximum Frequency Maximum Frequency Usage (High Performance mode) (Low Power mode) CK_SCU_SCU 13MHz 13MHz SCU Main CK_SCU_SCU_SC 13MHz 13MHz SCU Main CPU control only...
  • Page 250 CXD5602 User Manual  RCOSC (standard operating frequency of 8.13 MHz)  XOSC  CK_SCU_32K (RTC clock or RCOSC divided by 250) For the XOSC, frequency divisions of 1, 2, 3, or 4 can be selected by the CRG. However, since the maximum operating frequency of the SCU is 13 MHz, you will need to select the appropriate frequency division in accordance with the crystal oscillator that is connected from outside.
  • Page 251 CXD5602 User Manual CK_SCU_SPI For SPI CK_SCU_I2C0 For I2C0 CK_SCU_I2C1 For I2C1 CK_SCU_SEQ For sequencer CK_SCU_BRG_H For AHB bridge Directly connected from CK_SCU_32K For PWM timer Selector 1 The Clock Source Selector and frequency division circuit can be controlled from the TOPREG.
  • Page 252 CXD5602 User Manual provided to CK_SCU_SCU_SPI, CK_SCU_SCU_I2C1, and CK_SCU_SCU_I2C0 are controlled by the signal that is made by ORing dedicated bit in the SCU_CKEN: the signal from the upper layer, and the signal (2) from the internal sequencer of the SCU. Note that each control signal from the internal sequencer that is input to each clock’s control is independent.
  • Page 253 CXD5602 User Manual 3.9.4.6 Clock Control from Internal Sequencers To reduce power consumption, the firmware of the internal sequencers attempts to stop as many as clocks as possible during Sleep. Also, since SPI, I2C0, and I2C1 are master devices, each of their clocks are controlled by the internal sequencers so they operate only during data transfer (Table SCU (Sensor Control Unit)-94).
  • Page 254 CXD5602 User Manual Table SCU (Sensor Control Unit)-87 Clock Control from CPU Operation requested from Internal Register clock clock clock clock clock clock clock clock Access (incl. FIFO) (1*) RAM Access clock clock clock clock clock clock clock clock clock...
  • Page 255 CXD5602 User Manual 3.9.5 Power Supply Control The SCU module belongs to a power domain called PWD_SCU. Within the PWD_SCU, there are power supply control module regions (listed below) as separate power domains. Refer to the PMU Chapter (3.4) for details on the ON/OFF control registers of these power domains.
  • Page 256 CXD5602 User Manual one signal that is output as INT3. An interrupt mask can be separately set for each of the interrupt factors, and the statuses before and after the masks are applied can be read out. The Edge interrupt factor can be cleared. In addition, depending on the interrupt factor, Level/Edge selection is possible.
  • Page 257 CXD5602 User Manual Table SCU (Sensor Control Unit)-98 and Table SCU (Sensor Control Unit)-99 show the interrupt factors that are ORed within the SCU. Table SCU (Sensor Control Unit)-90 Information Interrupts Interrupt Name Number Description Edge/L evel LPADC_ALMO 4 (n = 0, ..., The data amount stored in the FIFO for the “n”...
  • Page 258 CXD5602 User Manual Table SCU (Sensor Control Unit)-91 System Error Interrupts Interrupt Name Number Description Edge/ Level LPADC_OVE The FIFO for the “n” th channel of the LPADC within the ADCIF has Edge R_RUNn 0, ..., 3) overflowed HPADCn_OV 2 (n = 1, 2) The FIFO for the “n”...
  • Page 259 CXD5602 User Manual Table SCU (Sensor Control Unit)-100 shows the interrupt factors received by the sequencers. Table SCU (Sensor Control Unit)-92 Interrupts for the Sequencers Interrupt Name Number Description EXE_REQ_STTn 10 (n = 0, ..., 9) Execution request to SEQn...
  • Page 260 CXD5602 User Manual REQ_BEFORE_FINISH This process was not in time by the next startup of the sequencer. A timeout error. 3.9.7 MATH_PROC processing The MATH_PROC processing performs programmable arithmetic processing to the data captured by the sensors. When using MATH_PROC processing, make sure that the data type is “Calculation Operable Sample Type”.
  • Page 261 CXD5602 User Manual Math function Math function Decim Math function Decim Math function Decim Figure SCU (Sensor Control Unit)-58 Decimation Partition Data Path ・Preprocessing can be performed to the 1, 2, or 3 axis data of the signed 16 bit.
  • Page 262 CXD5602 User Manual round clip unsigned_to_signed Offset Gain Figure SCU (Sensor Control Unit)-60 Preprocessing Data Flow As for offset addition and gain multiplication, when the data is multiple-axis (2 axis/3 axis), settings can be made independently for each X, Y, and Z axis.
  • Page 263 CXD5602 User Manual Level wrap wrap Level wrap wrap clip Shift Level wrap wrap clip Shift Level wrap wrap clip Shift Figure SCU (Sensor Control Unit)-61 Decimation Processing Data Flow 3.9.7.3 Math Function Processing 3.9.7.3.1 2nd Order IIR Filter The Math Function is a function block comprised of 2nd order IIR Filters, normalization processing, and excess detection.
  • Page 264 CXD5602 User Manual Excess Norm. Detector 2nd order 2nd order Figure SCU (Sensor Control Unit)-62 Data Flow within the Math Function The path on the top is output to the FIFO and the path on the bottom is used for excess detection.
  • Page 265 CXD5602 User Manual 4'b0001 4'b1000 2nd order 2nd order Excess 2nd order 2nd order Excess Norm. Norm. Detector Detector 4'b0010 4'b1001 2nd order 2nd order 2nd order Excess 2nd order Excess Norm. Norm. Detector Detector 4'b0011 4'b1010 2nd order 2nd order...
  • Page 266 CXD5602 User Manual round clip round shift shift clip round round round round Figure SCU (Sensor Control Unit)-64 2nd Order IIR Filter Internal Data Flow 3.9.7.3.2 Normalization Processing The normalization processing performs simplified conversion of multiple axis (2 axis/3 axis) data to single axis values.
  • Page 267 CXD5602 User Manual 3.9.7.3.3 Excess Detection The Excess Detection function performs excess detection to the value converted to 1 axis at the normalization processing and then outputs an interrupt to the upper module. Also, the result of this conversion can be used for writing control to the FIFO.
  • Page 268 CXD5602 User Manual dummy UCOUNT0 UCOUNT1 UTHRESH Upper Upper status in status in LTHRESH Lower Lower status in status in LCOUNT0 LCOUNT1 Upper Upper Upper Detect Detect Detect Lower Lower Lower Detect Detect Detect check the continuity of the status...
  • Page 269 CXD5602 User Manual E.g.: When UCOUNT0==2/UCOUNT1==4/DELAY_SMAPLE_R==0 A Rise interrupt occurs when Upper data is input two samples in a row, and Upper data continues for three samples after. When Upper data is input two samples in a row, and Lower data continues for LCOUNT0 times or more within three samples, the UCOUNT conditions are not referenced and the continuous match count of UCOUNT1 returns to its initial value.
  • Page 270 CXD5602 User Manual 3.9.7.4 FIFO Writing The following FIFO writing conditions can be set in conjunction with the interrupts generated by the excess detection function of the Math Function.  Stop writing by generating Rise/Fall interrupt ・Performs writing to the FIFO until an interrupt occurs, and after the interrupt, writes to the FIFO until a specified number of samples.
  • Page 271 CXD5602 User Manual 128-bit : 1 Sample format (16 Byte/Sample) 3.9.8.3 Partition The SRAM for the FIFO has up to 27 partitions. The partitions are classified as follows: … x 4 partitions x 2 sets (Total: 8 partitions) (1) Decimation Partitions (2) Normal Sensor Partitions …...
  • Page 272 CXD5602 User Manual N3_W_S N3_R0_H N3_R1_C Not Available Not Available N4_W_S N4_R0_H N4_R1_C Not Available Not Available N5_W_S N5_R0_H N5_R1_C Not Available Not Available N6_W_S N6_R0_H N6_R1_C Not Available Not Available N7_W_S N7_R0_H N7_R1_C Not Available Not Available virtual Sensor...
  • Page 273 CXD5602 User Manual 0x2024 N1_W_S 0x2124 N5_R1_C 0x2184 V9_R_H 0x2028 N2_W_S 0x2128 N6_R1_C 0x202C N3_W_S 0x212C N7_R1_C 0x2030 N4_W_S 0x2130 D0_R3_CH 0x2034 N5_W_S 0x2134 D1_R3_CH 0x2038 N6_W_S 0x2138 D0_R0_H 0x203C N7_W_S 0x213C D1_R1_H 0x2040 V0_W_C 0x2140 N0_R0_H 0x2044 V1_W_C 0x2144...
  • Page 274 CXD5602 User Manual  CPU dedicated readout port  Host dedicated readout port  CPU or Host readout port [Caution] The writing port and readout port must have a one-to-one relation. In the reset initial state, all readout ports are connected to the same readout port Dn_W0_S (n=0,1). Therefore, be sure to make the proper settings.
  • Page 275 CXD5602 User Manual  Valid data amount can be readout separately  Watermark Level (Almost Full) can be set separately  Interrupts/DMA transfer requests such as the following can be generated separately  When the valid data amount becomes equal to or higher than the Watermark, an interrupt is asserted, and when it falls below the Watermark, an interrupt is negated.
  • Page 276 CXD5602 User Manual Writing side (= latest) time stamp – (valid data samples – 1) x writing time interval 3.9.8.9 FIFO Block Diagram SCU_FIFO HandShake FIFO_REG Timestamp Decorder RAM I/F SRAM Figure SCU (Sensor Control Unit)-68 FIFO Block Diagram 3.9.8.10 FIFO Points of Attention ...
  • Page 277 CXD5602 User Manual Data Transfer Function  Reads the data from the I2C/SPI and transfers it to the FIFO ・Data can be transferred periodically according to the interrupt from the SCU_CTRL.  In accordance with the process request from the CPU, data can be read from the I2C/SPI (only one time) and transferred to the FIFO (One-shot Operation) ・Completion of the transfer is notified when the transfer completes.
  • Page 278 CXD5602 User Manual Among these processes, the Startup control is fully implemented in the hardware while the other operations are implemented in the software of the sequencer controller. There are 10 independent sequencers within the sequencer, each to which separate startup control and sensor polling settings are possible.
  • Page 279 CXD5602 User Manual D0_W0_S D0_R0_H D0_W1_S D0_R1_C D0_W2_S D0_R2_C SCU_RAM Sequencer SEQ0 D0_W3_S D0_R3_CH D1_W0_S D1_R0_H I2C0 SCU_RAM D1_W1_S D1_R1_C SEQ1 I2C1 D1_W2_S D1_R2_C SCU_RAM D1_W3_S D1_R3_CH SEQ2 LPADC0/1/2/3 SCU_RAM N0_W_S N0_R0_H ADCIF N0_R1_C SEQ3 HPADC0/1 N1_W_S N1_R0_H SCU_RAM N1_R1_C...
  • Page 280 CXD5602 User Manual 3.9.9.1 Startup Control SPI Master I2C Master 0 I2C Master 1 LPADC HPADC0 HPADC1 SEQUENCER 10 instruction group 3 instruction group Data MATH_PROC formatting request assertion of Generate signal Read Configuration Trigger Singal about request Sensor Control...
  • Page 281 CXD5602 User Manual 3.9.9.2 External Bus Transaction Generation SPI Master I2C Master 0 I2C Master 1 LPADC HPADC0 HPADC1 SEQUENCER 10 instruction group 3 instruction group Data MATH_PROC formatting request assertion of Generate signal Read Configuration Trigger Singal about request...
  • Page 282 CXD5602 User Manual 3.9.9.3 External Data Capture SPI Master I2C Master 0 I2C Master 1 LPADC HPADC0 HPADC1 SEQUENCER 10 instruction group 3 instruction group Data MATH_PROC formatting request assertion of Generate signal Read Configuration Trigger Singal about request Sensor...
  • Page 283 CXD5602 User Manual selected, the data is treated as 16 bit 2 axis data. When non-vector mode is selected, the data is treated as MSB-aligned 16 bit data for each channel. In the case of vector mode, the data readout from HPADC0 is allocated to the LSB side ({x}) and the data readout from HPADC1 is allocated to the MSB side ({y}).
  • Page 284 CXD5602 User Manual input data format (ex.12bit) Endian Stuffing MATH_WRITE_BYTE_SWAPT:0 data[0] data[1] [11:4] [3:0] [11:4] [3:0] [11:4] [3:0] MSB justified LSB MSB LSB MSB LSB MSB [11:4] [3:0] [11:8] [7:0] [11:8] [7:0] LSB justified LSB MSB LSB MSB LSB MSB...
  • Page 285 CXD5602 User Manual Calculation Inoperable Sample Type Calculation Operable Sample Type Firstly Read Data Lastly Read Data FIFO FIFO OUTPUT_8BIT:1 OUTPUT_8BIT:0 SCU_RAM SEQ_OUT_FORMAT 8bit x n 8bit x 2 x n Max 16Byte in the read order Figure SCU (Sensor Control Unit)-77 Data Stacked in the FIFO (Image) 3.9.9.4 Connectable Sequencers...
  • Page 286 CXD5602 User Manual when intentionally inserting a STOP command, an overhead of approximately 570 cycles (when RCOSC is 8.192 MHz) occurs due to resending the slave address. 3.9.9.4.2 The SPI can be connected to the any sequencer from SEQ0 to SEQ9.
  • Page 287 CXD5602 User Manual operation of writing the transfer data to the SEQ_RAM_OUT_n_READ_DATA_m (n is the One-shot Sequencer number n = 0, …, 2, m is the Byte offset of the data readout m = 0, …, 3, refer to Table SCU (Sensor Control Unit)-690) within the SCU_RAM is called “One-shot Operation”...
  • Page 288 CXD5602 User Manual UNSIGNED_TO_SIGNED Section 3.9.12.3.21 DEC_CLR Section 3.9.12.3.22 MATHFUNC_CLR Section 3.9.12.3.23 DECIMATION_PARAM* Section 3.9.12.3.25 and 3.9.12.3.26 MATHFUNC_SEL Section 3.9.12.3.27 MATHFUNC_POS* Section 3.9.12.3.28, 3.9.12.3.29, and 3.9.12.3.30 MATHFUNC_PARAM_* Section 3.9.12.3.31 to 3.9.12.3.96 EVENT_PARAM0_THRESH Section 3.9.12.3.97 EVENT_PARAM0_COUNT* Section 3.9.12.3.98, 3.9.12.3.99, and 3.9.12.3.100 EVENT_PARAM1_THRESH Section 3.9.12.3.101...
  • Page 289 CXD5602 User Manual D1_W1_S_CTRL* Section 3.9.12.10.26 and 3.9.12.10.27 D1_W2_S_CTRL* Section 3.9.12.10.31, and 3.9.12.10.32 D1_W3_S_CTRL* Section 3.9.12.10.36 and 3.9.12.10.37 N0_W_S_CTRL* Section 3.9.12.10.41 and 3.9.12.10.42 N1_W_S_CTRL* Section 3.9.12.10.46 and 3.9.12.10.47 N2_W_S_CTRL* Section 3.9.12.10.51 and 3.9.12.10.52 N3_W_S_CTRL* Section 3.9.12.10.56 and 3.9.12.10.57 N4_W_S_CTRL* Section 3.9.12.10.61 and 3.9.12.10.62 N5_W_S_CTRL* Section 3.9.12.10.66 and 3.9.12.10.67...
  • Page 290 CXD5602 User Manual V7_W_C_STATUS Section 3.9.12.10.132 V8_W_C_STATUS Section 3.9.12.10.139 V9_W_C_STATUS Section 3.9.12.10.146 SCU_REG D0_R1_C_ALMOST_FULL Section 3.9.12.3.125 D0_R2_C_ALMOST_FULL D1_R1_C_ALMOST_FULL D1_R2_C_ALMOST_FULL N0_R1_C_ALMOST_FULL N1_R1_C_ALMOST_FULL N2_R1_C_ALMOST_FULL N3_R1_C_ALMOST_FULL N4_R1_C_ALMOST_FULL N5_R1_C_ALMOST_FULL N6_R1_C_ALMOST_FULL N7_R1_C_ALMOST_FULL D0_R3_CH_ALMOST_FULL D1_R3_CH_ALMOST_FULL D0_R1_C_OVER_RUN Section 3.9.12.3.131 D0_R2_C_OVER_RUN D1_R1_C_OVER_RUN D1_R2_C_OVER_RUN N0_R1_C_OVER_RUN N1_R1_C_OVER_RUN N2_R1_C_OVER_RUN N3_R1_C_OVER_RUN N4_R1_C_OVER_RUN...
  • Page 291 CXD5602 User Manual N3_R1_C_UNDER_RUN N4_R1_C_UNDER_RUN N5_R1_C_UNDER_RUN N6_R1_C_UNDER_RUN N7_R1_C_UNDER_RUN D0_R3_CH_UNDER_RUN D1_R3_CH_UNDER_RUN Table SCU (Sensor Control Unit)-99 Parameters of I2C Resources Sub-resource Item Parameter Descriptions I2C_REG ----- Refer to the I2C (3.7) Chapter for information including the Parameters. Table SCU (Sensor Control Unit)-100 Parameters of SPI Resources...
  • Page 292 CXD5602 User Manual I2C0 MATH_PROC I2C1 FIFO Sequencer Processing Figure SCU (Sensor Control Unit)-78 Sequencer Data Flow Within the main loop, when a task of the I2C is called up for example, the I2C task will be executed as long as the sequencer number assigned to the I2C task is active.
  • Page 293 CXD5602 User Manual 3.9.9.10 Data Duplication Function By writing the COPY_ID as the copy destination and the COPY_ENALBE to the SCU_FIFO_COPY_INFO_n (n is sequencer number, 0 to 9) within SCU_RAM, the data is duplicated to the specified Write FIFO. The atomicity of the 3 axis data does not corrupt even when the duplication destination FIFO is dynamically switched during operation of the corresponding sequencer.
  • Page 294 CXD5602 User Manual sequencer completed one processing SEQ0 Processing START_CTRL interrupt Suspend request Figure SCU (Sensor Control Unit)-79 Sequencer Completed  “Operation suspended” refers to cases when one sequencer completes the processing of one main loop and waits for the next startup request (Figure SCU (Sensor Control Unit)-80).
  • Page 295 CXD5602 User Manual transition does not have to be checked). The judgement is “true” if the corresponding sequencer or ADC has been completed in accordance with the CPU request. 3.9.9.12.2 Suspension Judgement The following event notifies the suspension of operations.
  • Page 296 CXD5602 User Manual disables the IRQ3 interrupt mask, and waits for an interrupt. (4) Clears the interrupt factor, sets the IRQ3 interrupt mask, and sets HPADC1_ACCESS_INHIBIT_REQ to “0”. (5) Checks that the error flag (SCU_RAM internal parameter SYNCHRO_iSoP2CPU (refer to Section 3.9.12.11)) is not “1”.
  • Page 297 CXD5602 User Manual 3.9.9.12.4 Error Notification Error detection is performed when a suspend interrupt request is issued, and an error flag is set to the parameter (SYNCHRO_iSoP2CPU (refer to Section 3.9.12.11)) within the SCU_RAM when an error occurs. The conditions for error detection are as follows:...
  • Page 298 CXD5602 User Manual WAKEUP when the sequencer conditions are met. It is also possible to inhibit sequencers from entering SLEEP. The following shows the conditions of SLEEP, WAKEUP, and SLEEP inhibition. SLEEP Conditions The internal sequencer enters SLEEP when it satisfies all conditions below.
  • Page 299 CXD5602 User Manual Figure SCU (Sensor Control Unit)-83 DMA Handshake Signal Connections Table SCU (Sensor Control Unit)-109 shows the relation between the DMA request factors within the SCU and the 26 sets of handshake signals. Table SCU (Sensor Control Unit)-101 DMA Handshake Signals and Connection Destination DMAC ch IDs...
  • Page 300 CXD5602 User Manual LPADC (Ch.1) FIFO Rx (N1_R1_C) ch19 LPADC (Ch.2) FIFO Rx (N2_R1_C) ch20 LPADC (Ch.3) FIFO Rx (N3_R1_C) ch21 HPADC (Ch.0) ch10 FIFO Rx (N4_R1_C) ch22 HPADC (Ch.1) ch11 FIFO Rx (N5_R1_C) ch23 FIFO Rx (N6_R1_C) ch24 FIFO Rx (N7_R1_C) ch25 3.9.11...
  • Page 301 CXD5602 User Manual  PWMn_PARAM register PWMn_CYCLE field … sets the cycle  PWMn_PARAM register PWMn_THRESH field … sets the duty (L width)  PWMn_EN register PWMn_EN field … selects the permission of operation  PWMn_EN register PWM_SELLn field[2:0] … selects the ADC channel used as the reference ...
  • Page 302 CXD5602 User Manual Table SCU (Sensor Control Unit)-102 PWM Maximum and Minimum Setting Range SCU Frequency Prescaler Setting Output Variable Range (Setting Example) (representative Maximum Frequency Longest Cycle Pulse Width Accuracy example) (Duty 50%) 13 MHz 6.5 MHz (154 ns) 396.7 Hz (2.521 ms)
  • Page 303 CXD5602 User Manual Set PWMn_THRESH to “0” and select ENABLE + UPDATE fixed to Low Level Set ENABLE to “0”  Setting to make PMW Output fixed status (control at PWM combining point) Paste to H Set PWM_SEL_INVn to “0x1” and PWM_SEL_DISn to “0x1”...
  • Page 304 CXD5602 User Manual Enable control of this synchronization function is controlled by the PWMn_EN field of the PWMn_EN register and synchronization operation starts by using the Writing to the PWMn_UPDATE register as a trigger. The following is an example of the settings.
  • Page 305 CXD5602 User Manual α maximum value = (2^PWM_CNTENn) - 1 (1/2 --> 1[clk], 1/4 --> 3[clk], …, 1/256 --> 255[clk]) Note: This shift occurs randomly and cannot be controlled. 3.9.11.3.2 ADC-PWM Synchronization Settings Procedure (when you do not want to...
  • Page 306 CXD5602 User Manual PWM output Data Enable HPADC output (Channel 0) HPADC output (Channel 1) FIFO Write Capture timing is Timing controllable The number of capture data is controllable Figure SCU (Sensor Control Unit)-85 ADC Data Capture Mode using the PWM Output Timing as a Reference When setting the PWM channel n (n = 0, ..., 7), set the following registers in addition to the basic operation...
  • Page 307 CXD5602 User Manual the ADC side. Table SCU (Sensor Control Unit)-104 ADC Channels and PWM Assignment Register Name Field Name Target ADC LPADC_D1[20:12] DECI _RATIO2 LPADC0 LPADC_D4[20:12] DECI _RATIO2 LPADC1 LPADC_D5[20:12] DECI _RATIO2 LPADC2 LPADC_D6[20:12] DECI _RATIO2 LPADC3 HPADC_D0_D1[20:12] DECI _RATIO2...
  • Page 308 CXD5602 User Manual [3] Ch0 suspend PWM0_EN = 0x00000010 PWM0_UPDATE = 0x00000001 [4] Ch1 suspend PWM1_EN = 0x00000000 PWM1_UPDATE = 0x00000001 [5] Ch0 suspend and then process PWM_PASE0[15:0] = 0xffff [6] PWM another setting (if you want) The settings for the PWM you want to synchronize can be selected as follows:...
  • Page 309 CXD5602 User Manual 3.9.11.5.2 PWM Output Synchronization Initialization Procedures Note 1: Do not set PWM_PASEn[15:0] to “0xffff” nor “0x0000”. Note 2: “0xffff” is a setting for clear, and actual phase setting is not permitted. [1]PWM suspend setting PWM0_EN = 0x00000000...
  • Page 310 CXD5602 User Manual The setting of the PWM channel used for combining can be selected as follows: Table SCU (Sensor Control Unit)-106 Setting of PWM Channels to be Combined PWM_SEL_DISm[7:0] PWM0 Terminal PWM1 Terminal PWM2 Terminal PWM3 Terminal PWM_SEL_INVm[7:0] bit 0...
  • Page 311 CXD5602 User Manual 3.9.12 SCU Register Details 3.9.12.1 Address Offset The following shows 32 bit address offset from the CPU. Add the following address to the offsets in the table to calculate the address from the CPU. Offset: 0x00190000 (Mirror: 0x04190000) 3.9.12.2...
  • Page 312 CXD5602 User Manual When the bit is “0”, the operation of all sequencers is suspended. When the bit is “1”, the operation of each sequencer is performed according to the permission of each sequencer. 0x5024 SEQ_ACCESS_INHIBIT 0x00000000 0x5028 START_CTRL_COMMON 0x0000FF00...
  • Page 313 CXD5602 User Manual 5: D1_W1_S 6: D1_W2_S 7: D1_W3_S 8: N0_W_S 9: N1_W_S 10: N2_W_S 11: N3_W_S 12: N4_W_S 13: N5_W_S 14: N6_W_S 15: N7_W_S 0x5090 MATHFUNC_POS0 0x00000000 0x5094 MATHFUNC_POS1 0x00000000 0x5098 MATHFUNC_POS2 0x00000000 0x50A0 MATHFUNC_PARAM_0_0 0x00000000 0x50A4 MATHFUNC_PARAM_C0_0_ 0x00000000...
  • Page 314 CXD5602 User Manual 0_LSB 0x50E0 MATHFUNC_PARAM_0_1 0x00000000 0x50E4 MATHFUNC_PARAM_C0_0_ 0x00000000 1_MSB 0x50E8 MATHFUNC_PARAM_C0_0_ 0x00000000 1_LSB 0x50EC MATHFUNC_PARAM_C1_0_ 0x00000000 1_MSB 0x50F0 MATHFUNC_PARAM_C1_0_ 0x00000000 1_LSB 0x50F4 MATHFUNC_PARAM_C2_0_ 0x00000000 1_MSB 0x50F8 MATHFUNC_PARAM_C2_0_ 0x00000000 1_LSB 0x50FC MATHFUNC_PARAM_C3_0_ 0x00000000 1_MSB 0x5100 MATHFUNC_PARAM_C3_0_ 0x00000000 1_LSB 0x5104...
  • Page 315 CXD5602 User Manual 0_LSB 0x5130 MATHFUNC_PARAM_C4_1_ 0x00000000 0_MSB 0x5134 MATHFUNC_PARAM_C4_1_ 0x00000000 0_LSB 0x5138 MATHFUNC_PARAM_1_1 0x00000000 0x513C MATHFUNC_PARAM_C0_1_ 0x00000000 1_MSB 0x5140 MATHFUNC_PARAM_C0_1_ 0x00000000 1_LSB 0x5144 MATHFUNC_PARAM_C1_1_ 0x00000000 1_MSB 0x5148 MATHFUNC_PARAM_C1_1_ 0x00000000 1_LSB 0x514C MATHFUNC_PARAM_C2_1_ 0x00000000 1_MSB 0x5150 MATHFUNC_PARAM_C2_1_ 0x00000000 1_LSB 0x5154...
  • Page 316 CXD5602 User Manual 0_LSB 0x5180 MATHFUNC_PARAM_C3_2_ 0x00000000 0_MSB 0x5184 MATHFUNC_PARAM_C3_2_ 0x00000000 0_LSB 0x5188 MATHFUNC_PARAM_C4_2_ 0x00000000 0_MSB 0x518C MATHFUNC_PARAM_C4_2_ 0x00000000 0_LSB 0x5190 MATHFUNC_PARAM_2_1 0x00000000 0x5194 MATHFUNC_PARAM_C0_2_ 0x00000000 1_MSB 0x5198 MATHFUNC_PARAM_C0_2_ 0x00000000 1_LSB 0x519C MATHFUNC_PARAM_C1_2_ 0x00000000 1_MSB 0x51A0 MATHFUNC_PARAM_C1_2_ 0x00000000 1_LSB 0x51A4...
  • Page 317 CXD5602 User Manual 0x51DC EVENT_PARAM2_THRESH 0x00000000 0x51E0 EVENT_PARAM2_COUNT0 0x00000000 0x51E4 EVENT_PARAM2_COUNT1 0x00000000 0x51E8 EVENT_PARAM2_COUNT2 0x00000000 0x51EC EVENT_PARAM0_DELAY_S 0x00000000 AMPLE 0x51F0 EVENT_PARAM1_DELAY_S 0x00000000 AMPLE 0x51F4 EVENT_PARAM2_DELAY_S 0x00000000 AMPLE 0x5200 EVENT_TIMESTAMP0_R_M 0x00000000 0x5204 EVENT_TIMESTAMP0_R_LS 0x00000000 0x5208 EVENT_TIMESTAMP1_R_M 0x00000000 0x520C EVENT_TIMESTAMP1_R_LS 0x00000000 0x5210...
  • Page 318 CXD5602 User Manual 0x5408 INT_CLEAR_MAIN 0x00000000 0x540C LEVEL_SEL_MAIN 0x00000000 0x5410 INT_RAW_STT_MAIN 0x00000000 0x5414 INT_MASKED_STT_MAIN 0x00000000 0x5420 INT_ENABLE_ERR_0 0x00000000 0x5424 INT_DISABLE_ERR_0 0x00000000 0x5428 INT_CLEAR_ERR_0 0x00000000 0x542C INT_RAW_STT_ERR_0 0x00000000 0x5430 INT_MASKED_STT_ERR_0 0x00000000 0x5440 INT_ENABLE_ERR_1 0x00000000 0x5444 INT_DISABLE_ERR_1 0x00000000 0x5448 INT_CLEAR_ERR_1 0x00000000 0x544C...
  • Page 319 CXD5602 User Manual Pulse period/width setting 0x5610 PWM1_EN 0x00000000 0x5614 PWM1_UPDATE 0x00000000 0x5618 PWM2_PARAM 0x00000000 0x561C PWM2_EN 0x00000000 0x5620 PWM2_UPDATE 0x00000000 0x5624 PWM3_PARAM 0x00000000 0x5628 PWM3_EN 0x00000000 0x562C PWM3_UPDATE 0x00000000 0x5630 PWM_PASE0 0x00000000 0x5634 PWM_PASE1 0x00000000 0x5638 PWM_PASE2 0x00000000 0x563C...
  • Page 320 CXD5602 User Manual 0x56A4 POWER_EN 0x0000FFFF 3.9.12.3.1 {0x5018} I2C0 Details Table SCU (Sensor Control Unit)-109 Register Type: RO (read only) Local Address: 0x5018 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 321 CXD5602 User Manual 3.9.12.3.2 {0x501C} I2C1 Details Table SCU (Sensor Control Unit)-110 Register Type: RO (read only) Local Address: 0x501C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 322 CXD5602 User Manual 3.9.12.3.3 {0x5020} SEQ_ENABLE_ALL Details Permission/prohibition setting for operations of whole sequencers can be collectively controlled 0: operation is prohibited 1: operation is permitted When the bit is “0”, the operation of all sequencers is suspended. When the bit is “1”, the operation of each sequencer is performed according to the permission of each sequence.
  • Page 323 CXD5602 User Manual 3.9.12.3.4 {0x5024} SEQ_ACCESS_INHIBIT Details Table SCU (Sensor Control Unit)-112 Register Type: RW (read/write) Local Address: 0x5024 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 324 CXD5602 User Manual After “I2C1_ACCESS_INHIBIT_REQ==1” is detected, if you stop the I2C1 slave access, the sequencer sets “1” on I2C1_ACCESS_INH this bit. IBIT_ACK You must read or write on the register for I2C1 slave after the bit becomes “1”. After “I2C0_ACCESS_INHIBIT_REQ==1” is detected, if you stop the I2C0 slave access, the sequencer sets “1”...
  • Page 325 CXD5602 User Manual When the CPU directly accesses I2C1, “1” is set on this bit. SEQ_CTRL holds the access to I2C1 while the bit is “1”. I2C1_ACCESS_INH Note that if this bit is set “1” for longer time than the IBIT_REQ sequencer’s access cycle using I2C1 from SEQ_CTRL, the...
  • Page 326 CXD5602 User Manual 3.9.12.3.5 {0x5028} START_CTRL_COMMON Details Table SCU (Sensor Control Unit)-113 Register Type: RW (read/write) Local Address: 0x5028 Reset Value: 0x0000FF00 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 327 CXD5602 User Manual 3.9.12.3.6 {0x502C} START_MODE0 Details Table SCU (Sensor Control Unit)-114 Register Type: RW (read/write) Local Address: 0x502C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 328 CXD5602 User Manual This designates permission/prohibition Sequencer 4’s operation. Even if the operation is START_ENABLE4 RW permitted, when ENABLE_ALL is prohibited, the operation will not start. This designates permission/prohibition Sequencer 3’s operation. Even if the operation is START_ENABLE3 RW permitted, when ENABLE_ALL is prohibited, the operation will not start.
  • Page 329 CXD5602 User Manual 3.9.12.3.7 {0x5030} START_MODE1 Details Table SCU (Sensor Control Unit)-115 Register Type: RW (read/write) Local Address: 0x5030 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 330 CXD5602 User Manual 3.9.12.3.8 {0x5034} START_INTERVAL3_0 Details Table SCU (Sensor Control Unit)-116 Register Type: RW (read/write) Local Address: 0x5034 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 331 CXD5602 User Manual 7..4 Reserved Reserved This designates Sequencer 0’s timer operating frequency division value. START_IN When SEQ_MODE0 is “0” or “1”, this set value is referred. 3..0 TERVAL0 As for the calculating formula of the operating frequency, the range of values that can be set, and set values when using the One-shot Sequencer, refer to START_INTERVAL3.
  • Page 332 CXD5602 User Manual This designates Sequencer 5’s timer operating frequency division value. START_IN When SEQ_MODE5 is “0” or “1”, this set value is referred. 11..8 TERVAL5 As for the calculating formula of the operating frequency, the range of values that can be set, and set values when using the One-shot Sequencer, refer to START_INTERVAL3.
  • Page 333 CXD5602 User Manual This designates Sequencer 8’s timer operating frequency division value. START_I When SEQ_MODE8 is “0” or “1”, this set value is referred. 3..0 NTERVA As for the calculating formula of the operating frequency, the range of values that can be set, and set values when using the One-shot Sequencer, refer to START_INTERVAL3.
  • Page 334 CXD5602 User Manual 3.9.12.3.11 {0x5040} START_PHASE1_0 Details Table SCU (Sensor Control Unit)-119 Register Type: RW (read/write) Local Address: 0x5040 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 335 CXD5602 User Manual 3.9.12.3.12 {0x5044} START_PHASE3_2 Details Table SCU (Sensor Control Unit)-120 Register Type: RW (read/write) Local Address: 0x5044 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 336 CXD5602 User Manual 3.9.12.3.13 {0x5048} START_PHASE5_4 Details Table SCU (Sensor Control Unit)-121 Register Type: RW (read/write) Local Address: 0x5048 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 337 CXD5602 User Manual 3.9.12.3.14 {0x504C} START_PHASE7_6 Details Table SCU (Sensor Control Unit)-122 Register Type: RW (read/write) Local Address: 0x504C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 338 CXD5602 User Manual 3.9.12.3.15 {0x5050} START_PHASE9_8 Details Table SCU (Sensor Control Unit)-123 Register Type: RW (read/write) Local Address: 0x5050 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 339 CXD5602 User Manual 3.9.12.3.16 {0x5054} SINGLE_EXE Details Table SCU (Sensor Control Unit)-124 Register Type: RW (read/write) Local Address: 0x5054 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 340 CXD5602 User Manual By writing “1”, Sequencer 4’s execution request is issued only once. When the corresponding START_ENABLE bit is “0”, this register is REQ4 WO 0x0 not active. When SEQ_MODE4 is “2” or “3”, this set value is referred.
  • Page 341 CXD5602 User Manual 3.9.12.3.18 {0x505C} START_CTRL_STT1 Details Table SCU (Sensor Control Unit)-126 Register Type: RO (read only) Local Address: 0x505C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 342 CXD5602 User Manual 3.9.12.3.19 {0x5060} DEBUG_CTRL Details Table SCU (Sensor Control Unit)-127 Register Type: RW (read/write) Local Address: 0x5060 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 343 CXD5602 User Manual 3.9.12.3.20 {0x5070} OFST_GAIN_EN Details Table SCU (Sensor Control Unit)-128 Register Type: RW (read/write) Local Address: 0x5070 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 344 CXD5602 User Manual Designate “1” to perform offset addition processing and gain OFST_GAIN_ multiplication processing for MATH_PROC of Sequencer 2. If “0” is designated, the value of OFST_GAIN2 is ignored. 7..5 Reserved Reserved Designate “1” to perform offset addition processing and gain OFST_GAIN_ multiplication processing for MATH_PROC of Sequencer 1.
  • Page 345 CXD5602 User Manual 3.9.12.3.21 {0x5074} UNSIGNED_TO_SIGNED Details Table SCU (Sensor Control Unit)-129 Register Type: RW (read/write) Local Address: 0x5074 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 346 CXD5602 User Manual UNSIGNED_TO This controls processing of Sequencer 2. _SIGNED8 As for specifications, refer to UNSIGNED_TO_SIGNED15. 7..5 Reserved Reserved UNSIGNED_TO This controls processing of Sequencer 1. _SIGNED4 As for specifications, refer to UNSIGNED_TO_SIGNED15. 3..1 Reserved Reserved UNSIGNED_TO This controls processing of Sequencer 0.
  • Page 347 CXD5602 User Manual 3.9.12.3.22 {0x5078} DEC_CLR Details Table SCU (Sensor Control Unit)-130 Register Type: WO (write only) Local Address: 0x5078 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 348 CXD5602 User Manual 3.9.12.3.23 {0x507C} MATHFUNC_CLR Details Table SCU (Sensor Control Unit)-131 Register Type: WO (write only) Local Address: 0x507C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 349 CXD5602 User Manual 3.9.12.3.25 {0x5084} DECIMATION_PARAM0 Details Table SCU (Sensor Control Unit)-133 Register Type: RW (read/write) Local Address: 0x5084 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 350 CXD5602 User Manual Level adjust value setting with clipping for D1_W1_S. 13..12 LEVEL_ADJ_1 RW As for specifications, refer to LEVEL_ADJ_3. Decimation ratio for D0_W1_S. 11..8 As for specifications, refer to N3. 7..6 Reserved Reserved Level adjust value setting with clipping for D0_W0_S.
  • Page 351 CXD5602 User Manual 3.9.12.3.26 {0x5088} DECIMATION_PARAM1 Details Table SCU (Sensor Control Unit)-134 Register Type: RW (read/write) Local Address: 0x5088 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 352 CXD5602 User Manual Reserved Reserved Level adjust value setting with clipping for D1_W1_S. 13..12 LEVEL_ADJ_5 As for specifications, refer to LEVEL_ADJ_7. Decimation ratio for D1_W1_S. 11..8 As for specifications, refer to N7. 7..6 Reserved Reserved Level adjust value setting with clipping for D1_W0_S.
  • Page 353 CXD5602 User Manual 3.9.12.3.27 {0x508C} MATHFUNC_SEL Details 0: D0_W0_S 8: N0_W_S 1: D0_W1_S 9: N1_W_S 2: D0_W2_S 10: N2_W_S 3: D0_W3_S 11: N3_W_S 4: D1_W0_S 12: N4_W_S 5: D1_W1_S 13: N5_W_S 6: D1_W2_S 14: N6_W_S 7: D1_W3_S 15: N7_W_S Table SCU (Sensor Control Unit)-135...
  • Page 354 CXD5602 User Manual 3.9.12.3.28 {0x5090} MATHFUNC_POS0 Details Excess Norm. Detector 2nd order 2nd order Figure SCU (Sensor Control Unit)-86 Processing Block Overview In Figure SCU (Sensor Control Unit)-86, we call insertion IIR on the left side “IIR0”, insertion IIR on the right side “IIR1”.
  • Page 355 CXD5602 User Manual 31..4 Reserved 0x0000000 Reserved This designates the position where the IIR of 3..0 POS_0 Math Function 0 is inserted. 3.9.12.3.29 {0x5094} MATHFUNC_POS1 Details As for the positions where the IIRs are inserted, refer to Section 3.9.12.3.28 {0x5090} MATHFUNC_POS0.
  • Page 356 CXD5602 User Manual 3.9.12.3.31 {0x50A0} MATHFUNC_PARAM_0_0 Details Round Clip Round Expand Clip ±3bit shift ±3bit shift Round Round Round Round Figure SCU (Sensor Control Unit)-87 Filter Overview Table SCU (Sensor Control Unit)-139 Register Type: RW (read/write) Local Address: 0x50A0 Reset Value: 0x00000000...
  • Page 357 CXD5602 User Manual 3.9.12.3.32 {0x50A4} MATHFUNC_PARAM_C0_0_0_MSB Details The IIR Parameter for Math Function 0 Table SCU (Sensor Control Unit)-140 Register Type: RW (read/write) Local Address: 0x50A4 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 358 CXD5602 User Manual 3.9.12.3.34 {0x50B0} MATHFUNC_PARAM_C1_0_0_MSB Details The IIR Parameter for Math Function 0 Table SCU (Sensor Control Unit)-142 Register Type: RW (read/write) Local Address: 0x50B0 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 359 CXD5602 User Manual 3.9.12.3.36 {0x50B8} MATHFUNC_PARAM_C2_0_0_MSB Details The IIR Parameter for Math Function 0 Table SCU (Sensor Control Unit)-144 Register Type: RW (read/write) Local Address: 0x50B8 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 360 CXD5602 User Manual 3.9.12.3.38 {0x50D0} MATHFUNC_PARAM_C3_0_0_MSB Details The IIR Parameter for Math Function 0 Table SCU (Sensor Control Unit)-146 Register Type: RW (read/write) Local Address: 0x50D0 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 361 CXD5602 User Manual 3.9.12.3.40 {0x50D8} MATHFUNC_PARAM_C4_0_0_MSB Details The IIR Parameter for Math Function 0 Table SCU (Sensor Control Unit)-148 Register Type: RW (read/write) Local Address: 0x50D8 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 362 CXD5602 User Manual 3.9.12.3.42 {0x50E0} MATHFUNC_PARAM_0_1 Details The IIR Parameter for Math Function 0 Table SCU (Sensor Control Unit)-150 Register Type: RW (read/write) Local Address: 0x50E0 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 363 CXD5602 User Manual 3.9.12.3.43 {0x50E4} MATHFUNC_PARAM_C0_0_1_MSB Details The IIR Parameter for Math Function 0 Table SCU (Sensor Control Unit)-151 Register Type: RW (read/write) Local Address: 0x50E4 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 364 CXD5602 User Manual 3.9.12.3.45 {0x50EC} MATHFUNC_PARAM_C1_0_1_MSB Details The IIR Parameter for Math Function 0 Table SCU (Sensor Control Unit)-153 Register Type: RW (read/write) Local Address: 0x50EC Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 365 CXD5602 User Manual 3.9.12.3.47 {0x50F4} MATHFUNC_PARAM_C2_0_1_MSB Details The IIR Parameter for Math Function 0 Table SCU (Sensor Control Unit)-155 Register Type: RW (read/write) Local Address: 0x50F4 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 366 CXD5602 User Manual 3.9.12.3.49 {0x50FC} MATHFUNC_PARAM_C3_0_1_MSB Details The IIR Parameter for Math Function 0 Table SCU (Sensor Control Unit)-157 Register Type: RW (read/write) Local Address: 0x50FC Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 367 CXD5602 User Manual 3.9.12.3.51 {0x5104} MATHFUNC_PARAM_C4_0_1_MSB Details The IIR Parameter for Math Function 0 Table SCU (Sensor Control Unit)-159 Register Type: RW (read/write) Local Address: 0x5104 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 368 CXD5602 User Manual 3.9.12.3.53 {0x510C} MATHFUNC_PARAM_1_0 Details The IIR Parameter for Math Function 1 Refer to {0x50A0} MATHFUNC_PARAM_0_0 Details Table SCU (Sensor Control Unit)-161 Register Type: RW (read/write) Local Address: 0x510C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 369 CXD5602 User Manual 3.9.12.3.54 {0x5110} MATHFUNC_PARAM_C0_1_0_MSB Details The IIR Parameter for Math Function 1 Refer to {0x50A4} MATHFUNC_PARAM_C0_0_0_MSB Details Table SCU (Sensor Control Unit)-162 Register Type: RW (read/write) Local Address: 0x5110 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 370 CXD5602 User Manual 3.9.12.3.56 {0x5118} MATHFUNC_PARAM_C1_1_0_MSB Details The IIR Parameter for Math Function 1 Refer to {0x50B0} MATHFUNC_PARAM_C1_0_0_MSB Details Table SCU (Sensor Control Unit)-164 Register Type: RW (read/write) Local Address: 0x5118 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 371 CXD5602 User Manual 3.9.12.3.58 {0x5120} MATHFUNC_PARAM_C2_1_0_MSB Details The IIR Parameter for Math Function 1 Refer to {0x50B8} MATHFUNC_PARAM_C2_0_0_MSB Details Table SCU (Sensor Control Unit)-166 Register Type: RW (read/write) Local Address: 0x5120 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 372 CXD5602 User Manual 3.9.12.3.60 {0x5128} MATHFUNC_PARAM_C3_1_0_MSB Details The IIR Parameter for Math Function 1 Refer to {0x50D0} MATHFUNC_PARAM_C3_0_0_MSB Details Table SCU (Sensor Control Unit)-168 Register Type: RW (read/write) Local Address: 0x5128 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 373 CXD5602 User Manual 3.9.12.3.62 {0x5130} MATHFUNC_PARAM_C4_1_0_MSB Details The IIR Parameter for Math Function 1 Refer {0x50D8} MATHFUNC_PARAM_C4_0_0_MSB Details{0x50D8} MATHFUNC_PARAM_C4_0_0_MSB Details Table SCU (Sensor Control Unit)-170 Register Type: RW (read/write) Local Address: 0x5130 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 374 CXD5602 User Manual 3.9.12.3.64 {0x5138} MATHFUNC_PARAM_1_1 Details The IIR Parameter for Math Function 1 Refer to {0x50E0} MATHFUNC_PARAM_0_1 Details Table SCU (Sensor Control Unit)-172 Register Type: RW (read/write) Local Address: 0x5138 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 375 CXD5602 User Manual 3.9.12.3.65 {0x513C} MATHFUNC_PARAM_C0_1_1_MSB Details The IIR Parameter for Math Function 1 Refer to {0x50E4} MATHFUNC_PARAM_C0_0_1_MSB Details Table SCU (Sensor Control Unit)-173 Register Type: RW (read/write) Local Address: 0x513C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 376 CXD5602 User Manual 3.9.12.3.67 {0x5144} MATHFUNC_PARAM_C1_1_1_MSB Details The IIR Parameter for Math Function 1 Refer to {0x50EC} MATHFUNC_PARAM_C1_0_1_MSB Details Table SCU (Sensor Control Unit)-175 Register Type: RW (read/write) Local Address: 0x5144 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 377 CXD5602 User Manual 3.9.12.3.69 {0x514C} MATHFUNC_PARAM_C2_1_1_MSB Details The IIR Parameter for Math Function 1 Refer to {0x50F4} MATHFUNC_PARAM_C2_0_1_MSB Details Table SCU (Sensor Control Unit)-177 Register Type: RW (read/write) Local Address: 0x514C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 378 CXD5602 User Manual 3.9.12.3.71 {0x5154} MATHFUNC_PARAM_C3_1_1_MSB Details The IIR Parameter for Math Function 1 Refer {0x50FC} MATHFUNC_PARAM_C3_0_1_MSB Details_{0x50FC}_MATHFUNC_PARAM_C3_0_1_MSB_ Table SCU (Sensor Control Unit)-179 Register Type: RW (read/write) Local Address: 0x5154 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 379 CXD5602 User Manual 3.9.12.3.73 {0x515C} MATHFUNC_PARAM_C4_1_1_MSB Details The IIR Parameter for Math Function 1 Refer to {0x50FC} MATHFUNC_PARAM_C3_0_1_MSB Details Table SCU (Sensor Control Unit)-181 Register Type: RW (read/write) Local Address: 0x515C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 380 CXD5602 User Manual 3.9.12.3.75 {0x5164} MATHFUNC_PARAM_2_0 Details The IIR Parameter for Math Function 2 Refer to {0x50A0} MATHFUNC_PARAM_0_0 Details Table SCU (Sensor Control Unit)-183 Register Type: RW (read/write) Local Address: 0x5164 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 381 CXD5602 User Manual 3.9.12.3.76 {0x5168} MATHFUNC_PARAM_C0_2_0_MSB Details The IIR Parameter for Math Function 2 Refer to {0x50A4} MATHFUNC_PARAM_C0_0_0_MSB Details Table SCU (Sensor Control Unit)-184 Register Type: RW (read/write) Local Address: 0x5168 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 382 CXD5602 User Manual 3.9.12.3.78 {0x5170} MATHFUNC_PARAM_C1_2_0_MSB Details The IIR Parameter for Math Function 2 Refer {0x50B0} MATHFUNC_PARAM_C1_0_0_MSB Details_{0x50B0}_MATHFUNC_PARAM_C1_0_0_MSB_ Table SCU (Sensor Control Unit)-186 Register Type: RW (read/write) Local Address: 0x5170 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 383 CXD5602 User Manual 3.9.12.3.80 {0x5178} MATHFUNC_PARAM_C2_2_0_MSB Details The IIR Parameter for Math Function 2 Refer to{0x50B8} MATHFUNC_PARAM_C2_0_0_MSB Details Table SCU (Sensor Control Unit)-188 Register Type: RW (read/write) Local Address: 0x5178 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 384 CXD5602 User Manual 3.9.12.3.82 {0x5180} MATHFUNC_PARAM_C3_2_0_MSB Details The IIR Parameter for Math Function 2 Refer to {0x50D0} MATHFUNC_PARAM_C3_0_0_MSB Details Table SCU (Sensor Control Unit)-190 Register Type: RW (read/write) Local Address: 0x5180 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 385 CXD5602 User Manual 3.9.12.3.84 {0x5188} MATHFUNC_PARAM_C4_2_0_MSB Details The IIR Parameter for Math Function 2 Refer to {0x50D8} MATHFUNC_PARAM_C4_0_0_MSB Details Table SCU (Sensor Control Unit)-192 Register Type: RW (read/write) Local Address: 0x5188 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 386 CXD5602 User Manual 3.9.12.3.86 {0x5190} MATHFUNC_PARAM_2_1 Details The IIR Parameter for Math Function 2 Table SCU (Sensor Control Unit)-194 Register Type: RW (read/write) Local Address: 0x5190 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 387 CXD5602 User Manual 3.9.12.3.87 {0x5194} MATHFUNC_PARAM_C0_2_1_MSB Details The IIR Parameter for Math Function 2 Refer to {0x50E4} MATHFUNC_PARAM_C0_0_1_MSB Details Table SCU (Sensor Control Unit)-195 Register Type: RW (read/write) Local Address: 0x5194 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 388 CXD5602 User Manual 3.9.12.3.89 {0x519C} MATHFUNC_PARAM_C1_2_1_MSB Details The IIR Parameter for Math Function 2 Refer {0x50EC} MATHFUNC_PARAM_C1_0_1_MSB Details_{0x50EC}_MATHFUNC_PARAM_C1_0_1_MSB_ Table SCU (Sensor Control Unit)-197 Register Type: RW (read/write) Local Address: 0x519C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 389 CXD5602 User Manual 3.9.12.3.91 {0x51A4} MATHFUNC_PARAM_C2_2_1_MSB Details The IIR Parameter for Math Function 2 Refer {0x50F4} MATHFUNC_PARAM_C2_0_1_MSB Details_{0x50F4}_MATHFUNC_PARAM_C2_0_1_MSB_ Table SCU (Sensor Control Unit)-199 Register Type: RW (read/write) Local Address: 0x51A4 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 390 CXD5602 User Manual 3.9.12.3.93 {0x51AC} MATHFUNC_PARAM_C3_2_1_MSB Details The IIR Parameter for Math Function 2 Refer {0x50FC} MATHFUNC_PARAM_C3_0_1_MSB Details_{0x50FC}_MATHFUNC_PARAM_C3_0_1_MSB_ Table SCU (Sensor Control Unit)-201 Register Type: RW (read/write) Local Address: 0x51AC Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 391 CXD5602 User Manual 3.9.12.3.95 {0x51B4} MATHFUNC_PARAM_C4_2_1_MSB Details The IIR Parameter for Math Function 2 Refer {0x50FC} MATHFUNC_PARAM_C3_0_1_MSB Details_{0x50FC}_MATHFUNC_PARAM_C3_0_1_MSB_ Table SCU (Sensor Control Unit)-203 Register Type: RW (read/write) Local Address: 0x51B4 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 392 CXD5602 User Manual 3.9.12.3.97 {0x51BC} EVENT_PARAM0_THRESH Details Continuous Match Detection 0 Continuous Match Detection 1 Comparator status status input Data status (upper, lower) (upper, lower) (unsigned 16bit) (upper, lower) Threshold Level (top) Number of status continuity EVENT_PARAMX_THRESH: UTHRESH Number of status continuity...
  • Page 393 CXD5602 User Manual 3.9.12.3.98 {0x51C0} EVENT_PARAM0_COUNT0 Details Excess detection for Math Function 0 Table SCU (Sensor Control Unit)-206 Register Type: RW (read/write) Local Address: 0x51C0 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 394 CXD5602 User Manual 3.9.12.3.100 {0x51C8} EVENT_PARAM0_COUNT2 Details Excess detection for Math Function 0 Table SCU (Sensor Control Unit)-208 Register Type: RW (read/write) Local Address: 0x51C8 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 395 CXD5602 User Manual 3.9.12.3.101 {0x51CC} EVENT_PARAM1_THRESH Details Excess detection for Math Function 1 Table SCU (Sensor Control Unit)-209 Register Type: RW (read/write) Local Address: 0x51CC Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 396 CXD5602 User Manual 3.9.12.3.102 {0x51D0} EVENT_PARAM1_COUNT0 Details Excess detection for Math Function 1 Table SCU (Sensor Control Unit)-210 Register Type: RW (read/write) Local Address: 0x51D0 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 397 CXD5602 User Manual 3.9.12.3.104 {0x51D8} EVENT_PARAM1_COUNT2 Details Excess detection for Math Function 1 Table SCU (Sensor Control Unit)-212 Register Type: RW (read/write) Local Address: 0x51D8 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 398 CXD5602 User Manual 3.9.12.3.105 {0x51DC} EVENT_PARAM2_THRESH Details Excess detection for Math Function 2 Table SCU (Sensor Control Unit)-213 Register Type: RW (read/write) Local Address: 0x51DC Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 399 CXD5602 User Manual 3.9.12.3.106 {0x51E0} EVENT_PARAM2_COUNT0 Details Excess detection for Math Function 2 Table SCU (Sensor Control Unit)-214 Register Type: RW (read/write) Local Address: 0x51E0 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 400 CXD5602 User Manual 3.9.12.3.108 {0x51E8} EVENT_PARAM2_COUNT2 Details Excess detection for Math Function 2 Table SCU (Sensor Control Unit)-216 Register Type: RW (read/write) Local Address: 0x51E8 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 401 CXD5602 User Manual 3.9.12.3.109 {0x51EC} EVENT_PARAM0_DELAY_SAMPLE Details Table SCU (Sensor Control Unit)-217 Register Type: RW (read/write) Local Address: 0x51EC Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 402 CXD5602 User Manual 3.9.12.3.111 {0x51F4} EVENT_PARAM2_DELAY_SAMPLE Details Table SCU (Sensor Control Unit)-219 Register Type: RW (read/write) Local Address: 0x51F4 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 403 CXD5602 User Manual 3.9.12.3.112 {0x5200} EVENT_TIMESTAMP0_R_MSB Details Table SCU (Sensor Control Unit)-220 Register Type: RO (read only) Local Address: 0x5200 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 404 CXD5602 User Manual 3.9.12.3.114 {0x5208} EVENT_TIMESTAMP1_R_MSB Details Table SCU (Sensor Control Unit)-222 Register Type: RO (read only) Local Address: 0x5208 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 405 CXD5602 User Manual 3.9.12.3.116 {0x5210} EVENT_TIMESTAMP2_R_MSB Details Table SCU (Sensor Control Unit)-224 Register Type: RO (read only) Local Address: 0x5210 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 406 CXD5602 User Manual 3.9.12.3.118 {0x5218} EVENT_TIMESTAMP0_F_MSB Details Table SCU (Sensor Control Unit)-226 Register Type: RO (read only) Local Address: 0x5218 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 407 CXD5602 User Manual 3.9.12.3.120 {0x5220} EVENT_TIMESTAMP1_F_MSB Details Table SCU (Sensor Control Unit)-228 Register Type: RO (read only) Local Address: 0x5220 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 408 CXD5602 User Manual 3.9.12.3.122 {0x5228} EVENT_TIMESTAMP2_F_MSB Details Table SCU (Sensor Control Unit)-230 Register Type: RO (read only) Local Address: 0x5228 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 409 CXD5602 User Manual 3.9.12.3.124 {0x5230} FIFO_WRITE_CTRL Details Table SCU (Sensor Control Unit)-232 Register Type: RW (read/write) Local Address: 0x5230 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 410 CXD5602 User Manual 3.9.12.3.125 {0x5400} INT_ENABLE_MAIN Details Table SCU (Sensor Control Unit)-233 Register Type: RW (read/write) Local Address: 0x5400 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 411 CXD5602 User Manual D1_R1_C_ALMOST_FULL D0_R2_C_ALMOST_FULL D0_R1_C_ALMOST_FULL MATH_EVENT2_R MATH_EVENT1_R MATH_EVENT0_R HPADC1_ALMOST_FULL HPADC0_ALMOST_FULL LPADC_ALMOST_FULL I2C1 I2C0 Interrupt permission for the SPI or Math Function Event 0. The interrupt is permitted by writing “1”. Writing “0” cannot prohibit the interrupt. -411/1010-...
  • Page 412 CXD5602 User Manual 3.9.12.3.126 {0x5404} INT_DISABLE_MAIN Details Table SCU (Sensor Control Unit)-234 Register Type: RW (read/write) Local Address: 0x5404 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 413 CXD5602 User Manual D1_R1_C_ALMOST_FULL D0_R2_C_ALMOST_FULL D0_R1_C_ALMOST_FULL MATH_EVENT2_R MATH_EVENT1_R MATH_EVENT0_R HPADC1_ALMOST_FULL HPADC0_ALMOST_FULL LPADC_ALMOST_FULL I2C1 I2C0 Interrupt prohibition for the SPI. The interrupt is prohibited by writing “1”. Writing “0” cannot permit the interrupt. -413/1010-...
  • Page 414 CXD5602 User Manual 3.9.12.3.127 {0x5408} INT_CLEAR_MAIN Details Table SCU (Sensor Control Unit)-235 Register Type: WO (write only) Local Address: 0x5408 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 415 CXD5602 User Manual D0_R2_C_ALMOST_FULL WO 0x0 D0_R1_C_ALMOST_FULL WO 0x0 MATH_EVENT2_R WO 0x0 MATH_EVENT1_R WO 0x0 MATH_EVENT0_R WO 0x0 HPADC1_ALMOST_FULL WO 0x0 HPADC0_ALMOST_FULL WO 0x0 LPADC_ALMOST_FULL WO 0x0 2..0 Reserved WO 0x0 Reserved -415/1010-...
  • Page 416 CXD5602 User Manual 3.9.12.3.128 {0x540C} LEVEL_SEL_MAIN Details Table SCU (Sensor Control Unit)-236 Register Type: RW (read/write) Local Address: 0x540C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 417 CXD5602 User Manual 8..6 Reserved Reserved HPADC1_ALMOST_FULL HPADC0_ALMOST_FULL Set “1” when you want to use interrupt LPADC_ALMOST_FULL as a level interrupt. LPADC_ALMOST_FULL Set “0” when you use the interrupt as an edge detection. 2..0 Reserved Reserved -417/1010-...
  • Page 418 CXD5602 User Manual 3.9.12.3.129 {0x5410} INT_RAW_STT_MAIN Details Table SCU (Sensor Control Unit)-237 Register Type: RO (read only) Local Address: 0x5410 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 419 CXD5602 User Manual D0_R2_C_ALMOST_FULL D0_R1_C_ALMOST_FULL MATH_EVENT2_R MATH_EVENT1_R MATH_EVENT0_R HPADC1_ALMOST_FULL HPADC0_ALMOST_FULL LPADC_ALMOST_FULL I2C1 I2C0 The interrupt status of the SPI or Math Function Event 0 before masking -419/1010-...
  • Page 420 CXD5602 User Manual 3.9.12.3.130 {0x5414} INT_MASKED_STT_MAIN Details Table SCU (Sensor Control Unit)-238 Register Type: RO (read only) Local Address: 0x5414 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 421 CXD5602 User Manual D0_R2_C_ALMOST_FULL D0_R1_C_ALMOST_FULL MATH_EVENT2_R MATH_EVENT1_R MATH_EVENT0_R HPADC1_ALMOST_FULL HPADC0_ALMOST_FULL LPADC_ALMOST_FULL I2C1 I2C0 The interrupt status of the SPI or Math Function Event 0 after masking -421/1010-...
  • Page 422 CXD5602 User Manual 3.9.12.3.131 {0x5420} INT_ENABLE_ERR_0 Details Table SCU (Sensor Control Unit)-239 Register Type: RW (read/write) Local Address: 0x5420 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 423 CXD5602 User Manual D1_R1_C_OVER_RUN D0_R2_C_OVER_RUN D0_R1_C_OVER_RUN 8..7 Reserved Reserved ADCIF_READ_ERR HPADC1_OVER_RUN HPADC0_OVER_RUN LPADC_OVER_RUN LPADC_OVER_RUN3 LPADC_OVER_RUN2 LPADC_OVER_RUN1 -423/1010-...
  • Page 424 CXD5602 User Manual 3.9.12.3.132 {0x5424} INT_DISABLE_ERR_0 Details Table SCU (Sensor Control Unit)-240 Register Type: RW (read/write) Local Address: 0x5424 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 425 CXD5602 User Manual D1_R1_C_OVER_RUN D0_R2_C_OVER_RUN D0_R1_C_OVER_RUN 8..7 Reserved Reserved ADCIF_READ_ERR HPADC1_OVER_RUN HPADC0_OVER_RUN LPADC_OVER_RUN LPADC_OVER_RUN3 LPADC_OVER_RUN2 Interrupt permission of overrun error (write LPADC_OVER_RUN1 occurrence at FIFO Full) for LPADC -425/1010-...
  • Page 426 CXD5602 User Manual 3.9.12.3.133 {0x5428} INT_CLEAR_ERR_0 Details Table SCU (Sensor Control Unit)-241 Register Type: WO (write only) Local Address: 0x5428 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 427 CXD5602 User Manual 3.9.12.3.134 {0x542C} INT_RAW_STT_ERR_0 Details Table SCU (Sensor Control Unit)-242 Register Type: RO (read only) Local Address: 0x542C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 428 CXD5602 User Manual D0_R1_C_OVER_RUN 8..7 Reserved Reserved ADCIF_READ_ERR HPADC1_OVER_RUN HPADC0_OVER_RUN LPADC_OVER_RUN LPADC_OVER_RUN3 LPADC_OVER_RUN2 LPADC_OVER_RUN1 -428/1010-...
  • Page 429 CXD5602 User Manual 3.9.12.3.135 {0x5430} INT_MASKED_STT_ERR_0 Details Table SCU (Sensor Control Unit)-243 Register Type: RO (read only) Local Address: 0x5430 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8...
  • Page 430 CXD5602 User Manual D0_R1_C_OVER_RUN 8..7 Reserved Reserved ADCIF_READ_ERR HPADC1_OVER_RUN HPADC0_OVER_RUN LPADC_OVER_RUN LPADC_OVER_RUN3 LPADC_OVER_RUN2 LPADC_OVER_RUN1 -430/1010-...
  • Page 431 CXD5602 User Manual 3.9.12.3.136 {0x5440} INT_ENABLE_ERR_1 Details Table SCU (Sensor Control Unit)-244 Register Type: RW (read/write) Local Address: 0x5440 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8...
  • Page 432 CXD5602 User Manual 3.9.12.3.137 {0x5444} INT_DISABLE_ERR_1 Details Table SCU (Sensor Control Unit)-245 Register Type: RW (read/write) Local Address: 0x5444 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 433 CXD5602 User Manual 3.9.12.3.138 {0x5448} INT_CLEAR_ERR_1 Details Table SCU (Sensor Control Unit)-246 Register Type: WO (write only) Local Address: 0x5448 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 434 CXD5602 User Manual 3.9.12.3.139 {0x544C} INT_RAW_STT_ERR_1 Details Table SCU (Sensor Control Unit)-247 Register Type: RO (read only) Local Address: 0x544C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8...
  • Page 435 CXD5602 User Manual 3.9.12.3.140 {0x5450} INT_MASKED_STT_ERR_1 Details Table SCU (Sensor Control Unit)-248 Register Type: RO (read only) Local Address: 0x5450 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 436 CXD5602 User Manual 3.9.12.3.141 {0x5460} INT_ENABLE_ERR_2 Details Table SCU (Sensor Control Unit)-249 Register Type: RW (read/write) Local Address: 0x5460 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 437 CXD5602 User Manual REQ_BEFORE_FINISH1 RW Permission of interrupt for requesting the next REQ_BEFORE_FINISH0 RW operation before completion (Sequencer 0) -437/1010-...
  • Page 438 CXD5602 User Manual 3.9.12.3.142 {0x5464} INT_DISABLE_ERR_2 Details Table SCU (Sensor Control Unit)-250 Register Type: RW (read/write) Local Address: 0x5464 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 439 CXD5602 User Manual REQ_BEFORE_FINISH1 RW Permission of interrupt for requesting the next REQ_BEFORE_FINISH0 RW operation before completion (Sequencer 0) -439/1010-...
  • Page 440 CXD5602 User Manual 3.9.12.3.143 {0x5468} INT_CLEAR_ERR_2 Details Table SCU (Sensor Control Unit)-251 Register Type: WO (write only) Local Address: 0x5468 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 441 CXD5602 User Manual REQ_BEFORE_FINISH1 WO 0x0 Clear of interrupt for requesting the next REQ_BEFORE_FINISH0 WO 0x0 operation before completion (Sequencer 0) -441/1010-...
  • Page 442 CXD5602 User Manual 3.9.12.3.144 {0x546C} INT_RAW_STT_ERR_2 Details Table SCU (Sensor Control Unit)-252 Register Type: RO (read only) Local Address: 0x546C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 443 CXD5602 User Manual REQ_BEFORE_FINISH1 RO Interrupt status for requesting the next REQ_BEFORE_FINISH0 RO operation before completion (Sequencer 0, before masking) -443/1010-...
  • Page 444 CXD5602 User Manual 3.9.12.3.145 {0x5470} INT_MASKED_STT_ERR_2 Details Table SCU (Sensor Control Unit)-253 Register Type: RO (read only) Local Address: 0x5470 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 445 CXD5602 User Manual REQ_BEFORE_FINISH1 RO Interrupt status for requesting the next REQ_BEFORE_FINISH0 RO operation before completion (Sequencer 0, after masking) -445/1010-...
  • Page 446 CXD5602 User Manual 3.9.12.3.146 {0x5500} RAM_TEST Details Table SCU (Sensor Control Unit)-254 Register Type: RW (read/write) Local Address: 0x5500 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 447 CXD5602 User Manual 3.9.12.3.148 {0x5520} INT_ENABLE_MAIN_AD Details Table SCU (Sensor Control Unit)-256 Register Type: RW (read/write) Local Address: 0x5520 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 448 CXD5602 User Manual 3.9.12.3.149 {0x5524} INT_DISABLE_MAIN_AD Details Table SCU (Sensor Control Unit)-257 Register Type: RW (read/write) Local Address: 0x5524 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 449 CXD5602 User Manual 3.9.12.3.150 {0x5528} INT_CLEAR_MAIN_AD Details Table SCU (Sensor Control Unit)-258 Register Type: WO (write only) Local Address: 0x5528 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 450 CXD5602 User Manual 3.9.12.3.151 {0x552C} LEVEL_SEL_MAIN_AD Details Table SCU (Sensor Control Unit)-259 Register Type: RW (read/write) Local Address: 0x552C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 451 CXD5602 User Manual 3.9.12.3.152 {0x5530} INT_RAW_STT_MAIN_AD Details Table SCU (Sensor Control Unit)-260 Register Type: RO (read only) Local Address: 0x5530 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 452 CXD5602 User Manual 3.9.12.3.153 {0x5534} INT_MASKED_STT_MAIN_AD Details Table SCU (Sensor Control Unit)-261 Register Type: RO (read only) Local Address: 0x5534 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 453 CXD5602 User Manual 3.9.12.3.154 {0x5600} PWM0_PARAM Details Table SCU (Sensor Control Unit)-262 Register Type: RW (read/write) Local Address: 0x5600 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 454 CXD5602 User Manual 3.9.12.3.155 {0x5604} PWM0_EN Details 100: LPADC0 101: LPADC1 110: LPADC2 111: LPADC3 Table SCU (Sensor Control Unit)-263 Register Type: RW (read/write) Local Address: 0x5604 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 455 CXD5602 User Manual 3.9.12.3.156 {0x5608} PWM0_UPDATE Details Table SCU (Sensor Control Unit)-264 Register Type: RW (read/write) Local Address: 0x5608 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 456 CXD5602 User Manual 3.9.12.3.158 {0x5610} PWM1_EN Details Table SCU (Sensor Control Unit)-266 Register Type: RW (read/write) Local Address: 0x5610 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 457 CXD5602 User Manual 3.9.12.3.159 {0x5614} PWM1_UPDATE Details Table SCU (Sensor Control Unit)-267 Register Type: RW (read/write) Local Address: 0x5614 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 458 CXD5602 User Manual 3.9.12.3.161 {0x561C} PWM2_EN Details Table SCU (Sensor Control Unit)-269 Register Type: RW (read/write) Local Address: 0x561C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 459 CXD5602 User Manual 3.9.12.3.162 {0x5620} PWM2_UPDATE Details Table SCU (Sensor Control Unit)-270 Register Type: RW (read/write) Local Address: 0x5620 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 460 CXD5602 User Manual 3.9.12.3.164 {0x5628} PWM3_EN Details Table SCU (Sensor Control Unit)-272 Register Type: RW (read/write) Local Address: 0x5628 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 461 CXD5602 User Manual 3.9.12.3.165 {0x562C} PWM3_UPDATE Details Table SCU (Sensor Control Unit)-273 Register Type: RW (read/write) Local Address: 0x562C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 462 CXD5602 User Manual 3.9.12.3.166 {0x5630} PWM_PASE0 Details Table SCU (Sensor Control Unit)-274 Register Type: RW (read/write) Local Address: 0x5630 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 463 CXD5602 User Manual 3.9.12.3.167 {0x5634} PWM_PASE1 Details Table SCU (Sensor Control Unit)-275 Register Type: RW (read/write) Local Address: 0x5634 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 464 CXD5602 User Manual 3.9.12.3.168 {0x5638} PWM_PASE2 Details Table SCU (Sensor Control Unit)-276 Register Type: RW (read/write) Local Address: 0x5638 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 465 CXD5602 User Manual 3.9.12.3.169 {0x563C} PWM_PASE3 Details Table SCU (Sensor Control Unit)-277 Register Type: RW (read/write) Local Address: 0x563C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 466 CXD5602 User Manual 3.9.12.3.170 {0x5640} PWM4_PARM Details Table SCU (Sensor Control Unit)-278 Register Type: RW (read/write) Local Address: 0x5640 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 467 CXD5602 User Manual 3.9.12.3.171 {0x5644} PWM4_EN Details 100:LPADC0 101:LPADC1 110:LPADC2 111:LPADC3 Table SCU (Sensor Control Unit)-279 Register Type: RW (read/write) Local Address: 0x5644 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 468 CXD5602 User Manual 3.9.12.3.172 {0x5648} PWM4_UPDATE Details Table SCU (Sensor Control Unit)-280 Register Type: RW (read/write) Local Address: 0x5648 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 469 CXD5602 User Manual 3.9.12.3.173 {0x564C} PWM5_PARAM Details Table SCU (Sensor Control Unit)-281 Register Type: RW (read/write) Local Address: 0x564C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 470 CXD5602 User Manual 3.9.12.3.174 {0x5650} PWM5_EN Details Table SCU (Sensor Control Unit)-282 Register Type: RW (read/write) Local Address: 0x5650 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 471 CXD5602 User Manual 3.9.12.3.175 {0x5654} PWM5_UPDATE Details Table SCU (Sensor Control Unit)-283 Register Type: RW (read/write) Local Address: 0x5654 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 472 CXD5602 User Manual 3.9.12.3.176 {0x5658} PWM6_PARAM Details Table SCU (Sensor Control Unit)-284 Register Type: RW (read/write) Local Address: 0x5658 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 473 CXD5602 User Manual 3.9.12.3.177 {0x565C} PWM6_EN Details Table SCU (Sensor Control Unit)-285 Register Type: RW (read/write) Local Address: 0x565C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 474 CXD5602 User Manual 3.9.12.3.178 {0x5660} PWM6_UPDATE Details Table SCU (Sensor Control Unit)-286 Register Type: RW (read/write) Local Address: 0x5660 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 475 CXD5602 User Manual 3.9.12.3.179 {0x5664} PWM7_PARAM Details Table SCU (Sensor Control Unit)-287 Register Type: RW (read/write) Local Address: 0x5664 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 476 CXD5602 User Manual 3.9.12.3.180 {0x5668} PWM7_EN Details Table SCU (Sensor Control Unit)-288 Register Type: RW (read/write) Local Address: 0x5668 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 477 CXD5602 User Manual 3.9.12.3.181 {0x566C} PWM7_UPDATE Details Table SCU (Sensor Control Unit)-289 Register Type: RW (read/write) Local Address: 0x566C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 478 CXD5602 User Manual 3.9.12.3.182 {0x5670} PWM_PASE4 Details Table SCU (Sensor Control Unit)-290 Register Type: RW (read/write) Local Address: 0x5670 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 479 CXD5602 User Manual 3.9.12.3.183 {0x5674} PWM_PASE5 Details Table SCU (Sensor Control Unit)-291 Register Type: RW (read/write) Local Address: 0x5674 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 480 CXD5602 User Manual 3.9.12.3.184 {0x5678} PWM_PASE6 Details Table SCU (Sensor Control Unit)-292 Register Type: RW (read/write) Local Address: 0x5678 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 481 CXD5602 User Manual 3.9.12.3.185 {0x567C} PWM_PASE7 Details Table SCU (Sensor Control Unit)-293 Register Type: RW (read/write) Local Address: 0x567C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 482 CXD5602 User Manual 3.9.12.3.186 {0x5680} PWM_TIMER01 details When the PWM is not used, PWM generator can be used as a timer. In this case, counter values within the timer can be read. Table SCU (Sensor Control Unit)-294 Register Type: RO (read only)
  • Page 483 CXD5602 User Manual 3.9.12.3.188 {0x5688} PWM_TIMER45 Details When the PWM is not used, PWM generator can be used as a timer. In this case, counter values within the timer can be read. Table SCU (Sensor Control Unit)-296 Register Type: RO (read only)
  • Page 484 CXD5602 User Manual 3.9.12.3.190 {0x5690} PWM_FUNCSEL0 Details When synthesizing the PWM, you can designate the polarity of the source PWM (for PWM0-3). Table SCU (Sensor Control Unit)-298 Register Type: RW (read/write) Local Address: 0x5690 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 485 CXD5602 User Manual 3.9.12.3.192 {0x5698} PWM_FUCN2 Details When synthesizing the PWM, you can designate whether to use the PWM or not (for PWM0-3). Table SCU (Sensor Control Unit)-300 Register Type: RW (read/write) Local Address: 0x5698 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 486 CXD5602 User Manual 3.9.12.3.194 {0x56A0} PWM_FUNC4 Details You can select synthesis by ANDing or ORing PWMs (0: AND, 1: OR) Table SCU (Sensor Control Unit)-302 Register Type: RW (read/write) Local Address: 0x56A0 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 487 CXD5602 User Manual 3.9.12.3.195 {0x56A4} POWER_EN Details Prohibited setting Table SCU (Sensor Control Unit)-303 Register Type: RW (read/write) Local Address: 0x56A4 Reset Value: 0x0000FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 488 CXD5602 User Manual 3.9.12.3.196 {0x0 .. 0x3FFC} SEQ_IRAM Details Instruction RAM array for internal sequencer Refer to Section 3.9.12.11. Table SCU (Sensor Control Unit)-304 Memory Type: RW (read/write) Local Address: 0x0 Reset Value: 0xxxxxxxxx Bits Name Type Reset Value Description 31..0...
  • Page 489 CXD5602 User Manual 3.9.12.4 SCU_ADCIF_REG Register List The following describes 32 bit address offset from the CPU. For calculating the address from the CPU, add this address to each offset in the table. Offset:0x0018dc00 (Mirror:0x0418dc00) For the offset Address from 0x0200 to 0x03D4 of the ADCIF control registers, refer to Chapter of ADC (3.21).
  • Page 490 CXD5602 User Manual 3.9.12.6.1 {0x0} MATH_PROC_EXE Details Table SCU (Sensor Control Unit)-307 Register Type: RO (read only) Local Address: 0x0 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 491 CXD5602 User Manual 3.9.12.6.2 {0x4} WRITE_DATA_SET0 Details Table SCU (Sensor Control Unit)-308 Register Type: RW (read/write) Local Address: 0x4 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 492 CXD5602 User Manual 3.9.12.6.3 {0x8} WRITE_DATA_SET1 Details Table SCU (Sensor Control Unit)-309 Register Type: RW (read/write) Local Address: 0x8 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 493 CXD5602 User Manual 3.9.12.6.5 {0x10} WRITE_DATA_SET3 Details Table SCU (Sensor Control Unit)-311 Register Type: RW (read/write) Local Address: 0x10 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 494 CXD5602 User Manual 3.9.12.6.7 {0x18} WRITE_DATA_SET5 Details Table SCU (Sensor Control Unit)-313 Register Type: RW (read/write) Local Address: 0x18 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 495 CXD5602 User Manual 3.9.12.6.8 {0x80} READ_DATA_SET0 Details Table SCU (Sensor Control Unit)-314 Register Type: RO (read only) Local Address: 0x80 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 496 CXD5602 User Manual 3.9.12.6.9 {0x84} READ_DATA_SET1 Details Table SCU (Sensor Control Unit)-315 Register Type: RO (read only) Local Address: 0x84 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 497 CXD5602 User Manual 3.9.12.7 SCU_SEQ_REG Overview Only sequencers in the SCU can access these registers. The following describes 32 bit address offset which can be seen from the sequencer in the SCU. For calculating the address to access from the sequencer in the SCU, add this Offset: 0x0000e400 to each Offset Address (Transaction Port) in the table.
  • Page 498 CXD5602 User Manual 3.9.12.8.1 {0x0} EXTERNAL_STT0 Details Table SCU (Sensor Control Unit)-318 Register Type: RO (read only) Local Address: 0x0 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8...
  • Page 499 CXD5602 User Manual Indicates that one or more data exist in the FIFO for LPADC_NOT_EMPTY1 LPADC Indicates that one or more data exist in the FIFO for LPADC_NOT_EMPTY0 LPADC I2C1_ACTIVE Indicates the operation active status of I2C1 Indicates that the status is I2C1 TX_FIFO Empty, but a...
  • Page 500 CXD5602 User Manual 3.9.12.8.2 {0x4} EXTERNAL_STT1 Details Table SCU (Sensor Control Unit)-319 Register Type: RO (read only) Local Address: 0x4 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 501 CXD5602 User Manual 3.9.12.8.3 {0x8} START_CTRL Details Table SCU (Sensor Control Unit)-320 Register Type: WO (write only) Local Address: 0x8 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 502 CXD5602 User Manual 3.9.12.8.4 {0x10} ISOPSTT Details Table SCU (Sensor Control Unit)-321 Register Type: RW (read/write) Local Address: 0x10 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 503 CXD5602 User Manual 3.9.12.8.5 {0x14} ISOPINT Details Table SCU (Sensor Control Unit)-322 Register Type: RW (read/write) Local Address: 0x14 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 504 CXD5602 User Manual 3.9.12.8.6 {0x18} POWER_CTRL Details Table SCU (Sensor Control Unit)-323 Register Type: RW (read/write) Local Address: 0x18 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 505 CXD5602 User Manual 3.9.12.8.7 {0x20} TIME_STAMP_MSB Details Table SCU (Sensor Control Unit)-324 Register Type: RO (read only) Local Address: 0x20 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 506 CXD5602 User Manual 3.9.12.8.9 {0x40} ISOPMONOUT Details Table SCU (Sensor Control Unit)-326 Register Type: RW (read/write) Local Address: 0x40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 507 CXD5602 User Manual 3.9.12.8.10 {0x44} SCU_ISOP_POWER Details 0: CK_SCU 1: CK_SPI 2: CK_I2C0 3: CK_I2C1 Table SCU (Sensor Control Unit)-327 Register Type: RW (read/write) Local Address: 0x44 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 508 CXD5602 User Manual 3.9.12.9 SCU_FIFO_REG Overview Offset:0x00180000 (Mirror:0x04180000) The following describes 32 bit address offset from the CPU. For calculating the address from the CPU, add this Offset: 0x0000e400 to each Offset Address (Transaction Port) in the table. Offset: 0x0000e400 3.9.12.10...
  • Page 509 CXD5602 User Manual 0x90 D1_W0_S_TIMSTAMP1 0x00000000 0xA0 D1_W1_S_CTRL0 0xA0000000 0xA4 D1_W1_S_CTRL1 0x00000000 0xA8 D1_W1_S_STATUS 0x00000000 0xAC D1_W1_S_TIMSTAMP0 0x00000000 0xB0 D1_W1_S_TIMSTAMP1 0x00000000 0xC0 D1_W2_S_CTRL0 0xA0000000 0xC4 D1_W2_S_CTRL1 0x00000000 0xC8 D1_W2_S_STATUS 0x00000000 0xCC D1_W2_S_TIMSTAMP0 0x00000000 0xD0 D1_W2_S_TIMSTAMP1 0x00000000 0xE0 D1_W3_S_CTRL0 0xA0000000 0xE4...
  • Page 510 CXD5602 User Manual 0x188 N4_W_S_STATUS 0x00000000 0x18C N4_W_S_TIMSTAMP0 0x00000000 0x190 N4_W_S_TIMSTAMP1 0x00000000 0x1A0 N5_W_S_CTRL0 0xA0000000 0x1A4 N5_W_S_CTRL1 0x00000000 0x1A8 N5_W_S_STATUS 0x00000000 0x1AC N5_W_S_TIMSTAMP0 0x00000000 0x1B0 N5_W_S_TIMSTAMP1 0x00000000 0x1C0 N6_W_S_CTRL0 0xA0000000 0x1C4 N6_W_S_CTRL1 0x00000000 0x1C8 N6_W_S_STATUS 0x00000000 0x1CC N6_W_S_