Sony CXD5602 User Manual page 251

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The Clock Source Selector and frequency division circuit can be controlled from the TOPREG.
Figure SCU (Sensor Control Unit)-56 shows the clock system. The CK_SCU_32K shown in the Figure is used
for the LPADC and HPADC within the SCU.
RCOSC
1/250
8.192MHz
RTC
CKSEL_SCU.SEL_SCU_32K
XOSC
DIV
CKSEL_SCU.SCU_XTAL
"configure unavailable"
(1) control signal from the HOSTIFC sequencer
(2) control signal from the SCU sequencer
As shown in Figure SCU (Sensor Control Unit)-56, the clock signal provided to CK_SCU_SCU is controlled
by the signal that is made by ORing SCU_CKEN[0]: the signal from the upper layer, the signal (1) from the
internal sequencer of the HOSTIFC, and the signal (2) from the internal sequencer of the SCU. The clock signal
Directly connected from
Selector 1
RCRTC
0
1
0
1
2
3
CKSEL_SCU.SEL_SCU
Figure SCU (Sensor Control Unit)-56 Clock System
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CK_SCU_SPI
CK_SCU_I2C0
CK_SCU_I2C1
CK_SCU_SEQ
CK_SCU_BRG_H
CLK
CK_SCU_32K
SCU_CKEN[5]
CG
SCU_CKEN[0]
(1)
(2)
CG
SCU_CKEN[8]
CG
SCU_CKEN[3]
(2)
CG
SCU_CKEN[4]
(2)
CG
SCU_CKEN[2]
(2)
CG
SCU_CKEN[1]
(2)
CG
CXD5602 User Manual
For SPI
For I2C0
For I2C1
For sequencer
For AHB bridge
For PWM timer
SCU
CK_SCU_32K
CK_SCU_SCU
CK_SCU_BRG_HCLK
CK_SCU_SCU_SC
CK_SCU_SCU_SPI
CK_SCU_SCU_SEQ
CK_SCU_SCU_I2C1
CK_SCU_SCU_I2C0