Sony CXD5602 User Manual page 941

3
Clock Frequency Division for SPI Flash Controller
The frequency of the clock for the SPI Flash Controller is determined by the ck_cpu_bus frequency and the
register setting value. The following equations show the frequency division of the clock for the SPI Flash
Controller.

Frequency division of the clock for the SPI Flash Controller based on the ck_cpu_bus

ck_sfc_sfclk_gear

ck_sfc_hclk_low_gear
Note:
Refer to Table SYSIOP Clock and Reset Control-806 for the frequency division(D).
Table SYSIOP Clock and Reset Control-766 Frequency Division Setting of Clock for the SPI Flash Controller
CKDIV_CPU_DSP_BUS.SFC_HCLK_LOW
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Caution upon Setting the Frequency Division
When the SPI Flash Controller is not used, set CKDIV_CPU_DSP_BUS.SFC_HCLK_LOW to "0".
8
= frequency division(D)
= frequency division(D) x 2
Frequency
Division(D)
1
2
3
4
5
6
7
8
9
10
16
32
64
128
256
512
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CXD5602 User Manual