Sony CXD5602 User Manual page 907

APP_DSP
Application Processor
ADSP0
PID2 async
bridge
FPU
ITM DAP CTI
Cortex-M4
Core Interrupt
NVIC WIC
SysTick
Controller
Watch Dog
MPU
BUS
I D S
Address Converter
APP MAIN Bus : 32b Multi-Layer AHB
Exclusive Load/Store
APP SRAM
protection protection
(MID+po (MID+po
wer) wer)
SRAM SRAM
0 1 ・・・SRAM2 - SRAM9・・・
128KB 128KB
Debug
ADSP1-5
PID3-7
Input
Timer
Timer
protection
setting reg
protection protection
(MID+po (MID+po
wer) wer)
SRAM SRAM
10 11
128KB 128KB
SYSIOP Bus
Figure APP-104 APP_DSP Block Diagram
Crypto
ADMAC
(AES)
Generator
protection protection protection
(MID+po (MID+po (MID+po
wer) wer) wer)
APP SUB Bus : 32b Multi-Layer AHB
protection protection
(MID+po (MID+po
wer) wer)
async
bridge
Audio Imaging / 2D
－907/1010－
CXD5602 User Manual
Clock General General
Reset Purpose Purpose
Registers Registers
Bus Exclusive LD/ST PID
disable Sleep Monitor
Watch Dog reset
Ored
Bus Error
Cause
Registers
AHB to APB
protection
(MID)
protection protection protection protection protection
(MID+po (MID+po (MID+po (MID+po (MID+po
wer) wer) wer) wer)
Storage/Connectivity
Protction
Setting
Registers
AHB to APB
protection
(MID+po
wer) wer)