Sony CXD5602 User Manual page 29

CXD5602 User Manual
Table SPI-749 SPI0 register Descriptions ............................................................................................................. 876
Table SPI-750 SPI3 Register List .......................................................................................................................... 878
Table SPI-751 SPI3 Register Descriptions ............................................................................................................ 878
Table SPI-752 SPI4 Register List .......................................................................................................................... 880
Table SPI-753 SPI5 Register List .......................................................................................................................... 882
Table UART-758 XOSC (26 MHz), High Performance Mode ............................................................................. 884
Table UART-759 XOSC (26 MHz), Low Power Mode ........................................................................................ 884
Table UART-764 UART1 Register List ................................................................................................................ 885
Table UART-765 UART2 Register List ................................................................................................................ 886
Table APP-770 XOSC (26 MHz), High Performance Mode................................................................................. 895
Table APP-771 XOSC (26 MHz), Low Power Mode ........................................................................................... 895
Table APP-776Clock Division Ratio Setting Registers ......................................................................................... 898
Table APP-777 Clock Switching Registers ........................................................................................................... 898
Table APP-778 Clock Enable Registers ................................................................................................................ 899
Table APP-779 Clock Reset Generator Registers ................................................................................................. 900
Table APP-780 APP SRAM Tile Clock Gating Registers .................................................................................... 904
Table APP-781 Reset Control Registers ................................................................................................................ 906
Table APP-782 APP_DSP Function List ............................................................................................................... 908
Table APP-783 APP_DSP Register List ............................................................................................................... 909
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Table APP-784 Cortex -M4 processor with FPU Function List ........................................................................... 911
Table APP-785 Register List ................................................................................................................................. 912
Table APP-786 Processor List ............................................................................................................................... 912
Table APP-787 WDTRES Register List ................................................................................................................ 915
Table APP-788 SLEEPING Signal Register List .................................................................................................. 915
Table APP-789 Debug Function List..................................................................................................................... 916
Table APP-790 Address Conversion Registers ..................................................................................................... 921
Table APP-791 Exclusive Access Register ........................................................................................................... 924
Table SYSIOP Clock and Reset Control-796 XOSC (26 MHz), High Performance Mode .................................. 936
Table SYSIOP Clock and Reset Control-797 XOSC (26 MHz), Low Power Mode ............................................. 937
Table SYSIOP Clock and Reset Control-802 Clock Switching Status Registers .................................................. 938
Table SYSIOP Clock and Reset Control-803 System and I/O Processor Frequency Division Setting ................. 940
Table SYSIOP Clock and Reset Control-804 AHB Clock Frequency Division Setting ....................................... 940
Table SYSIOP Clock and Reset Control-805 APB Clock Frequency Division Setting ........................................ 940
Table SYSIOP Clock and Reset Control-806 Frequency Division Setting of Clock for the SPI Flash Controller 941
Table SYSIOP Clock and Reset Control-807 Frequency Division Setting Status Registers ................................. 942
Table SYSIOP Clock and Reset Control-808 Clock Enable Status Registers ....................................................... 946
Table SYSIOP Clock and Reset Control-809 Reset Control Registers ................................................................. 951
Table ADC-810 Sampling Rate Range Supported by the LPADC ....................................................................... 956
Table ADC-811 Sampling Rate Range Supported by the HPADC ....................................................................... 957
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