Sony CXD5602 User Manual page 489

3.9.12.4 SCU_ADCIF_REG Register List
The following describes 32 bit address offset from the CPU. For calculating the address from the CPU, add this
address to each offset in the table.
Offset:0x0018dc00 (Mirror:0x0418dc00)
For the offset Address from 0x0200 to 0x03D4 of the ADCIF control registers, refer to Chapter of ADC (3.21).
3.9.12.5 SCU_MATH_PROC_REG Overview
Only sequencers in the SCU can access this register.
The following describes 32 bit address offsets which can be seen from the sequencers in the SCU. For calculating
the address to access from the sequencer in the CPU, add this address to each offset in the table.
Offset:0x0000e000
3.9.12.6 SCU_MATH_PROC_REG Register List
Offset Address
(Transaction Port)
0x0
0x4
0x8
0xC
0x10
0x14
0x18
0x80
0x84
0x88
Table SCU (Sensor Control Unit)-306
Name Type
MATH_PROC_EXE RO
WRITE_DATA_SET0 RW
WRITE_DATA_SET1 RW
WRITE_DATA_SET2 RW
WRITE_DATA_SET3 RW
WRITE_DATA_SET4 RW
WRITE_DATA_SET5 RW
READ_DATA_SET0 RO
READ_DATA_SET1 RO
READ_DATA_SET2 WO
Size (bits) Description
32
32
32
32
32
32
32
32
32
32
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Reset Value
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000