Sony CXD5602 User Manual page 324

I2C1_ACCESS_INH
10
IBIT_ACK
I2C0_ACCESS_INH
9
IBIT_ACK
SPI_ACCESS_INHI
8
BIT_ACK
7..6 Reserved
HPADC1_ACCESS_
5
INHIBIT_REQ
HPADC0_ACCESS_
4
INHIBIT_REQ
LPADC_ACCESS_I
3
NHIBIT_REQ
After "I2C1_ACCESS_INHIBIT_REQ==1" is detected, if
you stop the I2C1 slave access, the sequencer sets "1" on
RO 0x0 this bit.
You must read or write on the register for I2C1 slave after
the bit becomes "1".
After "I2C0_ACCESS_INHIBIT_REQ==1" is detected, if
you stop the I2C0 slave access, the sequencer sets "1" on
RO 0x0 this bit.
You must read or write on the register for I2C0 slave after
the bit becomes "1".
After "SPI_ACCESS_INHIBIT_REQ==1" is detected, if
you stop the SPI slave access, the sequencer sets "1" on this
RO 0x0 bit.
You must read or write on the register for the SPI slave after
the bit becomes "1".
RO 0x0 Reserved
When the sequencer is requested to be suspended
Suspend interrupt is requested and canceled to the internal
sequencer.
RW 0x0
"1" is set when the sequencer is requested to be suspended.
"0" is set in the interrupt context.
Refer to Section 3.9.9.12.3
When the sequencer is requested to be completed or
suspended
Release and inhibition of the SLEEP for the internal
sequencer is performed.
RW 0x0
"1" is set when the sequencer is requested to be
completed/suspended.
"0" is set after the request is done.
Refer to Section 3.9.9.13.
When the sequencer is requested to be completed
Complete interrupt is requested and canceled to the internal
sequencer.
RW 0x0
"1" is set when the sequencer is requested to be completed.
"0" is set in the interrupt context.
Refer to Section 3.9.9.12.3.
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CXD5602 User Manual