Sony CXD5602 User Manual page 938

3.14.3.3.2 Register Descriptions
Table SYSIOP Clock and Reset Control-802 shows the clock switching status registers. Make sure to use RW
registers as RO registers.
Table SYSIOP Clock and Reset Control-762 Clock Switching Status Registers
Address Register
Name
0x041004CC CKSEL_S
YSIOP
Bit Field Type Bit
Name
Reserved RO [31:22]
SEL_FD_PLL RW [21:20]
Reserved RO [19:18]
SEL_FREQD RW [17:16]
IS
Reserved RO [15:14]
SEL_I2CS RW [13:12]
Reserved RO [11:9]
－938/1010－
Initial Description
Value
0 Reserved
2'b00
Indicated as SEL(5) in
Reset Control-116
FREQDISC clock source switching
2'b00: SYSPLL clock not divided
2'b01: SYSPLL clock divided by 2
2'b10: SYSPLL clock divided by 4
2'b11: SYSPLL clock divided by 4
0 Reserved
2'b00
Indicated as SEL(4) in
Reset Control-116
FREQDISC clock source switching
2'b00: RCOSC
2'b01: XOSC
2'b10: The frequency divided clock selected by
CKSEL_SYSIOP.SEL_FD_PLL
2'b11: Prohibited setting
0 Reserved
2'b00
Indicated as SEL(3) in
Reset Control-116
I2C3 clock source switching
2'b00: The clock selected by
CKSEL_SYSIOP.SEL_HOST2
2'b01: The frequency divided clock selected by
CKSEL_SCU.SEL_SCU_XTAL
2'b10: SYSPLL
2'b11: Prohibited setting
0 Reserved
CXD5602 User Manual
Figure SYSIOP Clock and
Figure SYSIOP Clock and
Figure SYSIOP Clock and