Cxd5602 Outline; Introduction; Features - Sony CXD5602 User Manual

CXD5602 Outline

2
2.1

Introduction

CXD5602GF/GG is a 32 bit RISC low power microprocessor solution for wearable applications. It is based on the
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Arm Cortex -M4 processor with FPU 32 bit RISC and It integrates Arm
for the system controller (power management, clock, reset) and I/O processor. It incorporates embedded 1.5
MByte of SRAM, 64 KByte of backup SRAM, and 256 KByte of I/O processor SRAM.
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The Arm Cortex -M4 processor with FPU and Arm
Unit, respectively, that is, the CPUs are powered off by internal power switches. Processor SRAMs are able to
retain data, and it's possible to restart processors quickly.
To provide optimized hardware performance for sensor fusion and audio processing services, the device integrates
ultra-low power GNSS Domain, Audio Codec Domain and Sensor Domain. Integrated Audio Codec Domain
supports digital noise cancelling and digital equalizer. Sensor Domain provides the specialized engine for sensor
processing.
Eliminating the need for a discrete sensor hub, these features enable various sensor applications (activity
recognition, voice recognition, etc.) low power audio applications such as music playback (MP3 decode,
Bluetooth A2DP, etc.) and hands-free communication (Bluetooth HFP).
2.2

Features

The features of CXD5602GF/GG are:

Application Processor
Arm ® Cortex ® -M4 processor with FPU 32 bit RISC
Operating frequency up to 156 MHz

1.5 MByte Application Memory

Application Multi-layer Bus
32 bit Multi-layer bus architecture
Application Domain for Arm
Connectivity, Storage and Image Block

Audio Codec
Digital Equalizer (DEQ)
Two I2S Interfaces supported
Unique Audio Data Format (Pulse Density Modulation) between CXD5602GF/GG and CXD5247GF

8 bit parallel Camera Interface supported

2D Graphics Acceleration
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Cortex -M0+ are power-gated by the Power Management
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Cortex -M4 processor with FPU 32 bit RISC, Audio Codec,
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CXD5602 User Manual
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Cortex -M0+ 32 bit RISC specifically