Sony CXD5602 User Manual page 508

3.9.12.9 SCU_FIFO_REG Overview
Offset:0x00180000 (Mirror:0x04180000)
The following describes 32 bit address offset from the CPU. For calculating the address from the CPU, add this
Offset: 0x0000e400 to each Offset Address (Transaction Port) in the table.
Offset: 0x0000e400
3.9.12.10 SCU_FIFO_REG Register List
Table SCU (Sensor Control Unit)-329 SCU_FIFO_REG Register List
Offset Address Name
(Transaction
Port)
0x0 D0_W0_S_CTRL0
0x4 D0_W0_S_CTRL1
0x8 D0_W0_S_STATUS
0xC D0_W0_S_TIMSTAMP0
0x10 D0_W0_S_TIMSTAMP1
0x20 D0_W1_S_CTRL0
0x24 D0_W1_S_CTRL1
0x28 D0_W1_S_STATUS
0x2C D0_W1_S_TIMSTAMP0
0x30 D0_W1_S_TIMSTAMP1
0x40 D0_W2_S_CTRL0
0x44 D0_W2_S_CTRL1
0x48 D0_W2_S_STATUS
0x4C D0_W2_S_TIMSTAMP0
0x50 D0_W2_S_TIMSTAMP1
0x60 D0_W3_S_CTRL0
0x64 D0_W3_S_CTRL1
0x68 D0_W3_S_STATUS
0x6C D0_W3_S_TIMSTAMP0
0x70 D0_W3_S_TIMSTAMP1
0x80 D1_W0_S_CTRL0
0x84 D1_W0_S_CTRL1
0x88 D1_W0_S_STATUS
0x8C D1_W0_S_TIMSTAMP0
Type Size (bits) Description
RW 32
RW 32
RO 32
RO 32
RO 32
RW 32
RW 32
RO 32
RO 32
RO 32
RW 32
RW 32
RO 32
RO 32
RO 32
RW 32
RW 32
RO 32
RO 32
RO 32
RW 32
RW 32
RO 32
RO 32
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CXD5602 User Manual
Reset Value
0xA0000000
0x00000000
0x00000000
0x00000000
0x00000000
0xA0000000
0x00000000
0x00000000
0x00000000
0x00000000
0xA0000000
0x00000000
0x00000000
0x00000000
0x00000000
0xA0000000
0x00000000
0x00000000
0x00000000
0x00000000
0xA0000000
0x00000000
0x00000000
0x00000000