Sony CXD5602 User Manual page 112

3.3 Interrupt
3.3.1 Overview and Features
The LSI has individual interrupt controllers for the SYSIOP, GNSS, and APP.
The 128 bit interrupt factors are connected to the CPUs of each SYSIOP, GNSS, and APP.
Interrupt requests are divided into two main categories: one is internal interrupt generated from each CPU core or
Peripheral, and another is external interrupt from I/O.
As external interrupts, signals from I/O can be used without any change, and results of event detection by GPIO
can be used as well.
System and I/O Processor
Interrupt factor
(I/O, SYSIOP, GNSS, APP)
GNSS DSP
Application Processor
semapho re
FIFO
SW INT
DEBUG
TIMER
WDT
WDTINT
WDTRES
SW INT
DEBUG
TIMER
WDT
WDTINT
WDTRES
DEBUG
TIMER
WDT
WDTINT
WDTRES
Figure Interrupt-25 Interrupt Connection Diagram
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Interrupt input Register
Cause3[31:16]
Cause3[15:14]
Cause3[13]
Cause3[9:8]
Cause1[19:17]
Cause1[20]
Cause1[21]
Cause1[22]
Cause1[23]
Cause1[24]
128
EN Reg
Interrupt input Register
Cause3[31:16]
Cause3[15:14]
Cause3[13]
Cause3[9:8]
Cause1[19:17]
Cause1[20]
Cause1[21]
Cause1[4]
EN Reg
Interrupt input Register
Interrupt input Register
Interrupt input Register
Interrupt input Register
Interrupt input Register
Interrupt input Register
Cause3[31:16]
Cause3[15:14]
Cause3[0]
Cause2[13:12]
Cause3[3:1]
Cause3[4]
Cause3[5]
EN Reg
CXD5602 User Manual
WDTRESOUT
System Reset
(to CRG)
Cortex-M0+
PID0
NMI
32
IRQ
Cortex-M4
PID1
NMI
128
IRQ
Cortex-M4
PIDn
(n:2-7)
NMI
128
IRQ