Sony CXD5602 User Manual page 929

3.13.4.16.2 Power Supply ON for PWD_APP_DSP
For power supply control, refer to the PMU chapter 3.4.
3.13.4.16.3 ADSP Startup
Control the ADSP startup using System and I/O Processor or ADSP other than the target ADSP.
Note: about <N>
E.g., ADSP0 means that N = 0, ADSP1 means that N = 1, in the same way, ADSP5 means that N = 5.
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Precondition
The power supply of the power domain PWD_APP and PWD_APP_DSP must be ON. (For power
supply control, refer to the PMU chapter 3.4.)
1. Clock division ratio setting
GEAR_AHB.gear_m_ahb= arbitrary (division ratio denominator write)
GEAR_AHB.gear_n_ahb= arbitrary (division ratio numerator write)
2. Clock supply (Initialization of internal circuit)
CK_GATE_AHB.ck_gate_dsp<N>=1
3. Clock stop
CK_GATE_AHB.ck_gate_dsp<N>=0
4. ADSP start preparation
Transfer the program codes to the APP SRAM, and do the address converter setting.
(For address converter, refer to 3.13.4.13 section.)
5. Reset release
RESET.xrs_dsp<N>=1
6. Clock supply
CK_GATE_AHB.ck_gate_dsp<N>=1
3.13.4.16.4 Clock Frequency Change
1. Clock division ratio setting
GEAR_AHB.gear_m_ahb= (division ratio denominator)
GEAR_AHB.gear_n_ahb= (division ratio numerator)
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CXD5602 User Manual