Clock Architecture - Sony CXD5602 User Manual

2.7.2

Clock Architecture

The figure below shows CX5602 clock diagram. The CXD5602 has main five clock domains according to
functional blocks. Clock can be selected in accordance with the operating conditions of each functional block.

Always On

The RTC clock and the RCOSC clock can be selected.

Application Domain

The Application Processor can change the frequency dynamically with the frequency divider.

System and IOP Domain

Four clock sources: the SYSPLL, the XOSC, the RCOSC, and the RTC can be selected, and can be
switched dynamically in accordance with the use case.

The System and I/O Processor can change the frequency dynamically with the frequency divider.

Sensor Domain

Three clock sources: the RTC, XOSC, and RCOSC can be selected.

GNSS Domain

The clock selected by the System and I/O Processor in the System and IOP Domain is distributed
to the GNSS DSP. Frequency division ratio can be set independently.

The clock generated by either the SYSPLL or the RFPLL is distributed to the baseband signal
processing block. Operational constraints depend on which PLL is selected. For details, refer to
Chapter of the GNSS.
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CXD5602 User Manual