Sony CXD5602 User Manual page 162

3.5.3.3 SYSPLL Block Setting Confirmation
The frequencies of SYSPLL can be confirmed by the XOSC frequency and division ratio setting register as shown
in Table Clock and Reset (Clock Reset Generator)-53.
Table Clock and Reset (Clock Reset Generator)-53 SYSPLL Frequency Confirmation
XOSC
Frequency
[MHz]
16.368
19.2
26
32.736
52
3.5.3.3.1 Register Descriptions
Table Clock and Reset (Clock Reset Generator)-54 shows the control registers related to the SYSPLL block.
Table Clock and Reset (Clock Reset Generator)-54 SYSPLL Block Status Registers
Address Register
Name
0x04100588 SYS_PLL
_CTRL1
0x0410058C SYS_PLL
SYS_PLL_CTRL2.ISP_L
V_SELRCDIV[1:0]
0
0
1
0
1
1
1
1
3
3
Bit Field Type
Name
Reserved RW
ISP_LV_ENDSPCLK RW
Reserved RW
ISP_LV_ENGPADC RW
CLK
Reserved RW
ISP_LV_SELRCDIV RW
－162/1010－
SYS_PLL_CTRL2.ISP_L
V_SELFBDIV[2:0]
0
1
2
0
1
2
0
1
1
2
Bit Initial Description
Value
[31:4] 0 Reserved
[3] 0
Indicated as ANA(7) in
Reset (Clock Reset Generator)-34
Clock Enable for each function block
0: Clock supplied, 1: Clock stopped
[2] 0 Reserved
[1] 0 Indicated as ANA(6) in
Reset (Clock Reset Generator)-34
Clock Enable for GNSS
0: Clock supplied, 1: Clock stopped
[0] 0 Reserved
[31:30] 0 RCDIV frequency division ratio switching
CXD5602 User Manual
SYSPLL
Frequency
[MHz]
163.68
196.42
144.00
192.00
156.00
195.00
163.68
196.42
156.00
195.00
Figure Clock and
Figure Clock and