Sony CXD5602 User Manual page 249

3.9.4 Clock Control
3.9.4.1 Clock Summary
Clock Name
CK_SCU_SCU
CK_SCU_SCU_SC
CK_SCU_SCU_SPI
CK_SCU_SCU_I2C0
CK_SCU_SCU_I2C1
CK_SCU_SCU_SEQ
CK_SCU_XOSC
CK_SCU_RC8M
CK_SCU_U32KL
CK_SCU_U32KH
CK_SCU_32K
CK_SCU_BRG_HCLK
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For details on the clocks for the HPADC and LPADC, refer to the Chapter on ADC (3.21).
3.9.4.2 Logic System (High Speed) Clocks

CK_SCU_SCU

CK_SCU_SCU_SC

CK_SCU_SPI (for SPI)

CK_SCU_I2C0 (for I2C0)

CK_SCU_I2C1 (for I2C1)

CK_SCU_SEQ (for SEQ)

CK_SCU_BRG_HCLK
The above Logic System (High Speed) Clocks all have the same operating frequency (they are synchronized)
but their control conditions for clock enabler are different.
The Logic System (High Speed) Clocks are generated from one of the below clock sources at CRG (Clock and
Reset Generator) outside the SCU.
Table SCU (Sensor Control Unit)-82 Clock Summary
Maximum Frequency
(High Performance mode)
13MHz
13MHz
13MHz
13MHz
13MHz
13MHz
13MHz
8MHz
32kHz
32kHz
32kHz
13MHz
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Maximum Frequency Usage
(Low Power mode)
13MHz SCU Main
13MHz SCU Main CPU control only
13MHz For SPI
13MHz For I2C0
13MHz For I2C1
13MHz For SCU internal sequencer
13MHz For HPADC
8MHz For HPADC
32kHz For LPADC
32kHz For HPADC
32kHz For PWM
13MHz For AHB BUS
CXD5602 User Manual
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