Sony CXD5602 User Manual page 7

CXD5602 User Manual
Figure PMU (Power Management Unit)-31 PMU Clock System ......................................................................... 125
Figure PMU (Power Management Unit)-32 Sleep/Wakeup Control Flow of the Application Processor ............. 157
Figure Clock and Reset (Clock Reset Generator)-33 CRG Control Area within Overall Clock Scheme ............. 159
Figure Clock and Reset (Clock Reset Generator)-34 CRG Clock Scheme ........................................................... 159
Figure RTC-35 RTC0/1 Power Supply Framework .............................................................................................. 170
Figure RTC-36 Clock Resources of RTC .............................................................................................................. 172
Figure RTC-37 RTC Block Diagram..................................................................................................................... 173
Figure RTC-38 RTC (Time Update) Block Diagram ............................................................................................ 174
Figure I2C-39 I2C0/I2C1 Clock and Reset System ............................................................................................... 214
Figure I2C-40 I2C2 Clock and Reset System ........................................................................................................ 216
Figure I2C-41 I2C4 Clock and Reset System ........................................................................................................ 218
Figure DMAC-42 SDMAC Overview of Added Functions .................................................................................. 222
Figure DMAC-43 SDMAC Clock and Reset System............................................................................................ 224
Figure DMAC-44 HDMAC Overview of Added Functions ................................................................................. 225
Figure DMAC-45 HDMAC Clock and Reset System ........................................................................................... 226
Figure DMAC-46 SYDMAC Clock and Reset System ......................................................................................... 227
Figure DMAC-47 SYSUBDMAC Clock and Reset System ................................................................................. 229
Figure DMAC-48 ADMAC Clock and Reset System ........................................................................................... 230
Figure DMAC-49 IDMAC Function Block Diagram ............................................................................................ 231
Figure DMAC-50 IDMAC Clock and Reset System ............................................................................................ 242
Figure SCU (Sensor Control Unit)-51 Block Function Overview ......................................................................... 245
Figure SCU (Sensor Control Unit)-52 Memory Mapping from the Upper CPUs; the CPU in the SYSIOP and the
CPU in the GNSS; (hereinafter in the Chapter on SCU, referred as "upper CPUs") ........................................ 246
Figure SCU (Sensor Control Unit)-53 Memory Mapping within the SCU as seen from the Upper CPUs ........... 247
Figure SCU (Sensor Control Unit)-54 Memory Mapping as seen from the Internal Sequencer ........................... 248
Figure SCU (Sensor Control Unit)-55 Memory Mapping as seen from the HOSTIFC ........................................ 248
Figure SCU (Sensor Control Unit)-56 Clock System ............................................................................................ 251
Figure SCU (Sensor Control Unit)-57 Interrupt Connections ............................................................................... 256
Figure SCU (Sensor Control Unit)-58 Decimation Partition Data Path ................................................................ 261
Figure SCU (Sensor Control Unit)-59 Normal Sensor Partition Data Path ........................................................... 261
Figure SCU (Sensor Control Unit)-60 Preprocessing Data Flow .......................................................................... 262
Figure SCU (Sensor Control Unit)-61 Decimation Processing Data Flow ........................................................... 263
Figure SCU (Sensor Control Unit)-62 Data Flow within the Math Function ........................................................ 264
Figure SCU (Sensor Control Unit)-63 2 2nd Order IIR Filter Combinations........................................................ 265
Figure SCU (Sensor Control Unit)-64 2nd Order IIR Filter Internal Data Flow ................................................... 266
Figure SCU (Sensor Control Unit)-65 Normalization Processing Data Flow ....................................................... 266
Figure SCU (Sensor Control Unit)-66 Excess Detection Operation (by a Comparator and an Excess Detector) . 267
Figure SCU (Sensor Control Unit)-67 Excess Detection Operation (Two-step Cascade Connection) ................. 268
Figure SCU (Sensor Control Unit)-68 FIFO Block Diagram ................................................................................ 276
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