Sony CXD5602 User Manual page 242

3.8.8.3 Clock and Reset
Figure DMAC-50 shows the clock and reset system diagram of the IDMAC.
RTC_CLK_IN(32.768kHz)
SYSPLL
1/2
1/3
1/4
1/5
APP_CKSEL.APP_PLL_DIV5
APP_CKSEL.STAT_SP_CLK_SEL4
APP_CKSEL.STAT_APP_CLK_SEL4
APP_CKEN.APP
3.8.8.4 Clock Supply Start and Stop
3.8.8.4.1 Clock Supply Start
Perform the following control to start supplying the HCLK clock of the IDMAC.
1. Reset release
PWD_RESET0.PWD_APP=1'b1
RESET.xrs_img=1'b1
2. Supply the CK_APP (Refer to APP (Chapter 3.13))
3. AHB bus clock supply and division ratio setting
GEAR_AHB.gear_m_ahb= (arbitrary: denominator setting of the division ratio)
GEAR_AHB.gear_n_ahb= (arbitrary: numerator setting of the division ratio)
CK_GATE_AHB.ck_gate_dmac=1'b1
3.8.8.4.2 Clock Supply Stop
Perform the following control to stop supplying the HCLK clock of the IDMAC.
1. AHB bus clock stop
CK_GATE_AHB.ck_gate_img=1'b0
RCOSC
0
1
CK_APP
2 CK
XOSC
GATE
3
0
1
2
3
CK_GATE_AHB.ck_gate_dmac
0
1
CK_GATE_AHB.ck_gate_img
Figure DMAC-50 IDMAC Clock and Reset System
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GEAR_AHB.gear_m_ahb
GEAR_AHB.gear_n_ahb
RESET.xrs_dsp_gen
RESET.xrs_img
RST_APP_X
PWD_RESET0.PWD_APP
CXD5602 User Manual
N/M
CK
GATE
HCLK
HRESETn
CK
GATE
HCLK
HRESETn
ADMAC
IDMAC