Sony CXD5602 User Manual page 935

3.14.3 Clock and Reset Control
Using clock control, clock switching, frequency control by frequency division switching, and clock supply/stop
can be performed. Using reset control, reset assert/release of each block can be performed. The API is used for the
control.
3.14.3.1 SYSIOP Clock Configuration Diagram
Figure SYSIOP Clock and Reset Control-116 shows the SYSIOP clock configuration diagram. Within the figure,
the SEL(number), DIV(number), and CG(SYS/SUB number) are linked to the numbers within Table SYSIOP
Clock and Reset Control-802, Table SYSIOP Clock and Reset Control-807, and Table SYSIOP Clock and Reset
Control-808. For areas where the register names are directly indicated in the figure, refer to the descriptions in
each corresponding Section.
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CXD5602 User Manual