Sony CXD5602 User Manual page 167

3.5.5.1 Register Descriptions
Table Clock and Reset (Clock Reset Generator)-58 shows the reset registers of the power domain. There is a
Write Enable for each reset control bit, and reset control is performed for only the power domain to which "1" has
been written to the Write Enable.
Table Clock and Reset (Clock Reset Generator)-58 Reset Registers of the Power Domain
Address Register
Name
0x04100060 PWD_RE
SET0
3.5.6 Reset by WDT
3.5.6.1 Function Details
By detecting the asserting of the WDT within the System and I/O Processor, a reset is automatically issued to each
block of the CXD5602. However, reset by the WDT is not performed for the following registers or SRAM. (Reset
is performed only during POR).
Bit Field Type
Name
WEN RO
WO
Reserved RO
PWD_GNSS RW
PWD_GNSS_ITP RW
Reserved RO
PWD_APP RW
Reserved RO
PWD_SYSIOP_SUB RW
Reserved RO
PWD_SCU RW
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Bit Initial Description
Value
[31:30] 0 Reserved
[29] 0 Write Enable (PWD_GNSS)
[28] 0 Write Enable (PWD_GNSS_ITP)
[27:25] 0 Reserved
[24] 0 Write Enable (PWD_APP)
[23] 0 Reserved
[22] 0 Write Enable (PWD_SYSIOP_SUB)
[21:17] 0 Reserved
[16] 0 Write Enable (PWD_SCU)
[15:14] 0 Reserved
[13] 0 Reset of PWD_GNSS power domain
0: Reset is performed
1: Reset release
[12] 0 Reset of PWD_GNSS_ITP power domain.
[11:9] 0 Reserved
[8] 0 Reset of PWD_APP power domain
[7] 0 Reserved
[6] 1 Reset of PWD_SYSIOP_SUB power domain
[5:1] 0 Reserved
[0] 0 Reset of PWD_SCU power domain
CXD5602 User Manual