Sony CXD5602 User Manual page 6

Figure Contents
Figure Block Diagram-1 CXD5602 Block Diagram ............................................................................................... 36
Figure Memory Mapping-2 Memory Map of the SYSIOP, GNSS, and APP ......................................................... 40
Figure Clock and Reset-3 Clock Diagram ............................................................................................................... 47
Figure Power Management-4 Power Domain Layers .............................................................................................. 48
Figure Power Management-5 CXD5602 Power Domain ........................................................................................ 49
Figure Power Management-6 Changes of Power Supply States.............................................................................. 52
Figure I/O Configuration-7 Switching between HOST I/F Function and SWD Function....................................... 54
Figure I/O Configuration-8 Visualized Function inside IOCELL Controlled by IOCELL Control Register ......... 66
Figure I/O Configuration-9 Examples of Assigning Roles to the Pin (P1r_02) ...................................................... 70
Figure I/O Configuration-10 PMIC_INT Signal Routes (MODE=1) ...................................................................... 72
Figure I/O Configuration-11 PMIC_INT Signal Routes (MODE=2 Open Drain) .................................................. 73
Figure I/O Configuration-12 RTC_IRQ_OUT Signal Routes (MODE=2 Open Drain) .......................................... 74
Figure I/O Configuration-13 SDIO CLK Input Schematic ...................................................................................... 82
Figure I/O Configuration-14 SDIO WP/CD Input Control Register Schematic ...................................................... 83
Figure General Purpose Input/Output (GPIO)-15 GPIO Overview Block Diagram ............................................... 87
Figure General Purpose Input/Output (GPIO)-16 Diagram of GPIO Event Detect Block ...................................... 88
Figure General Purpose Input/Output (GPIO)-17 Output Signal Route in the I/O Function Controlled by GPIO
Parameter ............................................................................................................................................................. 91
Figure General Purpose Input/Output (GPIO)-18 Input Signal Route in the I/O Function Controlled by GPIO
Parameter ............................................................................................................................................................. 92
Figure General Purpose Input/Output (GPIO)-19 GPIO Pin Selection ................................................................... 93
Figure General Purpose Input/Output (GPIO)-20 External Interrupt Selection ...................................................... 97
Figure General Purpose Input/Output (GPIO)-21 Event Detection Control .......................................................... 100
Figure General Purpose Input/Output (GPIO)-22 Event Detection Timing Diagram ........................................... 103
Figure General Purpose Input/Output (GPIO)-23 Connection Diagram of Event Detection and SYSCPU or DSP
........................................................................................................................................................................... 108
Figure General Purpose Input/Output (GPIO)-24 Time Interval for a Signal to be able to Detect an Event Again
(PMU_WAKE_TRIG_NOISECUTEN0:0) ....................................................................................................... 111
Figure Interrupt-25 Interrupt Connection Diagram ............................................................................................... 112
Figure PMU (Power Management Unit)-26 PMU and the Power Domain Layers ............................................... 116
Figure PMU (Power Management Unit)-27 Individual Power Supply Control within the Power Domains ......... 118
Figure PMU (Power Management Unit)-28 Power Supply Control within the Power Domain (PWD_APP Main
Memory) ............................................................................................................................................................ 119
Figure PMU (Power Management Unit)-29 Changes of Power Supply States ..................................................... 121
Figure PMU (Power Management Unit)-30 Overall Block Diagram of the PMU ................................................ 124
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CXD5602 User Manual