Sony CXD5602 User Manual page 318

0x5408 INT_CLEAR_MAIN
0x540C LEVEL_SEL_MAIN
0x5410 INT_RAW_STT_MAIN
0x5414 INT_MASKED_STT_MAIN
0x5420 INT_ENABLE_ERR_0
0x5424 INT_DISABLE_ERR_0
0x5428 INT_CLEAR_ERR_0
0x542C INT_RAW_STT_ERR_0
0x5430 INT_MASKED_STT_ERR_0
0x5440 INT_ENABLE_ERR_1
0x5444 INT_DISABLE_ERR_1
0x5448 INT_CLEAR_ERR_1
0x544C INT_RAW_STT_ERR_1
0x5450 INT_MASKED_STT_ERR_1
0x5460 INT_ENABLE_ERR_2
0x5464 INT_DISABLE_ERR_2
0x5468 INT_CLEAR_ERR_2
0x546C INT_RAW_STT_ERR_2
0x5470 INT_MASKED_STT_ERR_2
0x5500 RAM_TEST
0x5510 SCU_POWER
0x5520 INT_ENABLE_MAIN_AD
0x5524 INT_DISABLE_MAIN_AD
0x5528 INT_CLEAR_MAIN_AD
0x552C LEVEL_SEL_MAIN_AD
0x5530 INT_RAW_STT_MAIN_AD
0x5534 INT_MASKED_STT_MAIN_
AD
0x5600 PWM0_PARAM
0x5604 PWM0_EN
0x5608 PWM0_UPDATE
0x560C PWM1_PARAM
WO 32
RW 32
RO 32
RO 32
RW 32
RW 32
WO 32
RO 32
RO 32
RW 32
RW 32
WO 32
RO 32
RO 32
RW 32
RW 32
WO 32
RO 32
RO 32
RW 32
RO 32 Clock status controlled by the SCU
internal sequencer
0: CK_SCU
1: CK_SCU_SPI
2: CK_SCU_I2C0
3: CK_SCU_I2C1
RW 32
RW 32
WO 32
RW 32
RO 32
RO 32
RW 32 PWM0
Pulse period/width setting
RW 32
RW 32
RW 32 PWM1
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CXD5602 User Manual
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