Sony CXD5602 User Manual page 911

3.13.4.4 Cortex
The APP_DSP equips six Cortex
endianness of the processor, byte lanes in the little endian are used.
Table APP-784 describes the functions of the Cortex
Function
Memory Protection Unit (MPU)
Floating Point Unit (FPU)
Nested Vectored Interrupt Controller (NVIC)
Wakeup Interrupt Controller (WIC)
WIC Support Signal
Trace Support Level
Debug Support Level
Bit-band
For Intellectual Property cores (IP cores) offered by ARM Limited, refer to the following references.

® ®
Arm Cortex -M4 Processor Technical Reference Manual

®
Cortex -M4 Devices Generic User Guide

ARMv7-M Architecture Reference Manual
®
-M4 processor with FPU
®
-M4 processors with FPU. On the APP_DSP Bus Matrix, regardless of the
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Table APP-752 Cortex -M4 processor with FPU Function List
Description
Memory Protection Unit is equipped. It can control eight independent areas.
A calculation function of single precision floating point number is supported.
The NVIC supports 128 interrupts.
The priority of each interrupt can be set in 256 steps.
Wakeup Interrupt Controller (WIC) is equipped.
The WIC interface uses NMI, EDBGRQ, RXEV, and IRQ[127:0] to detect
Wakeup Interrupts.
The ITM, TPIU, DWT trigger, and counter are supported. The ETM and
HTM are not supported.
All debug functions except for data matching are supported.
A bit-band function is not supported in this system.
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-M4 processor with FPU.
CXD5602 User Manual