Sony CXD5602 User Manual page 163

_CTRL2
3.5.4 Clock Setting Confirmation
3.5.4.1 Register Descriptions
The following describes the status confirmation registers of the clock switching and the clock Enable. Some of
them are RW registers, but use them as RO registers.
3.5.4.1.1 Clock Switching
Table Clock and Reset (Clock Reset Generator)-55 shows the status registers of clock switching.
Table Clock and Reset (Clock Reset Generator)-55 Clock Switching Status Registers
Address Register
Name
0x041004C4 CKSEL_
ROOT
ISP_LV_SELFBDIV RW
Reserved RW
Bit Field Type
Name
PMU_STAT_CLK_S RO
EL4
Reserved RW
STAT_CLK_SEL4 RO
Reserved RW
－163/1010－
[29:27] 3'b001 FBDIV frequency division ratio switching
[26:0] 0 Reserved
Bit Initial Description
Value
[31:30] 0
Indicated as SEL(5) in
Reset (Clock Reset Generator)-34
PMU's clock source switching status
2'b00: RCRTC (frequency of dividing the
RCOSC by 250)
2'b01: Reserved
2'b10: RTC Clock
2'b11: Reserved
[29:24] 0 Reserved
[23:22] 0
Indicated as SEL(4) in
Reset (Clock Reset Generator)-34
Clock source switching status for System and
I/O Processor/AHB/APB
2'b00: RCOSC
2'b01: SYSPLL
2'b10: XOSC
2'b11: RTC Clock
[21:14] 0 Reserved
CXD5602 User Manual
Figure Clock and
Figure Clock and