Sony CXD5602 User Manual page 914

Application Processor
ADSP0
WDT
WDTINT
WDTRES
ADSP1
WDT
WDTINT
WDTRES
ADSP2
WDT
WDTINT
WDTRES
ADSP3
WDT
WDTINT
WDTRES
ADSP4
WDT
WDTINT
WDTRES
ADSP5
WDT
WDTINT
WDTRES
All the WDTRES signal status of the ADSP can be confirmed by reading the registers.
Interrupt input
Register
Interrupt input
Register
Interrupt input
Register
Interrupt input
Register
Interrupt input
Register
Interrupt input
Register
WD_TIM_RES[5:0]
Figure APP-105 WDTRES Connection
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CXD5602 User Manual
Cortex-M4
128
(PID2)
IRQ
NMI
Cortex-M4
128
(PID3)
IRQ
NMI
Cortex-M4
128
(PID4)
IRQ
NMI
Cortex-M4
128
(PID5)
IRQ
NMI
Cortex-M4
128
(PID6)
IRQ
NMI
Cortex-M4
128
(PID7)
IRQ
NMI
to System and I/O Processor