Sony CXD5602 User Manual page 879

3.10.3.3 Clock and Reset
Figure SPI-97 shows the clock and reset system diagram of the SPI3.
When accessing the SPI3 register, set SCU_CKEN.SCU=1'b1 beforehand.
RCOSC
RTC_CLK_IN
(32.768kHz)
CKSEL_SCU.SEL_SCU_32K
XOSC
CKSEL_SCU.SEL_SCU_XTAL
CKSEL_SCU.SEL_SCU
3.10.3.4 Clock Supply Start and Stop
3.10.3.4.1 Clock Supply Start
Perform the following control to start supplying the SSPCLK clock and PCLK clock to the SPI3.
1. Reset release
SWRESET_SCU.XRST_SCU_SPI=1'b1
2. Clock supply start
SCU_CKEN.SCU_SPI=1'b1
3.10.3.4.2 Clock Supply Stop
Perform the following control to stop supplying the SSPCLK clock and PCLK clock to the SPI3.
1. Clock supply stop
SCU_CKEN.SCU_SPI=1'b0
slave_type RW
1/250
0
1
Reserved
0
1/2 1
1/3
2
1/4
3
Figure SPI-97 SPI3 Clock and Reset System
－879/1010－
[1:0] 2'b00 SPI communication slave selection function
0,3: SPI3_CS0_X
1: SPI3_CS1_X
2: SPI3_CS2_X
0
1
ck_scu_pre
2
SCU_CKEN.SCU_SPI
3
PWD_RESET0.PWD_SCU
SWRESET_SCU.XRST_SCU_SPI
CXD5602 User Manual
SPI3
CK
SSPCLK
GATE
PCLK
nSSPRST
PRESETn