Architecture Overview - Sony CXD5602 User Manual

CXD5602 User Manual
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Architecture Overview

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The CXD5602 has one Arm Cortex -M0 and seven Arm Cortex -M4 (includes FPU) inside. Each CPU is
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connected each other through multi-layer AHB matrixes and bus bridges separately. Arm Cortex -M0 is inside
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the SYSIOP. One Arm Cortex -M4 is prepared for the GNSS only, and the remainder six Arm Cortex -M4 for
the APP.
The CXD5602 has a bus architecture using the Bus Matrix so that eight CPUs and the other bus masters can
independently access to each slave, not affected by any bus traffic.
By Round-robin arbitration inside the Bus Matrix, bus master need not to wait for a long time to access to slave
even if access competition occurs.
As Figure Block Diagram-1 shows, each bus in the APP/SYSIOP/GNSS is independent.
In addition, between the SYSIOP and the GNSS, and between the SYSIOP and the APP, each peripheral is
connected to the bus bridge.
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