Sony CXD5602 User Manual page 252

provided to CK_SCU_SCU_SPI, CK_SCU_SCU_I2C1, and CK_SCU_SCU_I2C0 are controlled by the signal
that is made by ORing dedicated bit in the SCU_CKEN: the signal from the upper layer, and the signal (2) from
the internal sequencer of the SCU. Note that each control signal from the internal sequencer that is input to each
clock's control is independent.
The clock signal provided to CK_SCU_SCU_SEQ is controlled by the signal that is made by ANDing
SCU_CKEN[4]: the signal from the upper layer, and the signal (2) from the internal sequencer of the SCU.
As this described, the clocks within the SCU are divided into several domains, and clock control is possible from
the SYSCPU, DSP, internal sequencer of the HOSTIFC, or the internal sequencer of the SCU. In the case of
controlling from multiple CPUs/internal sequencers, OR control is used.
SCU Clock Name
CK_SCU_SCU
CK_SCU_SCU_SC
CK_SCU_SCU_SPI
CK_SCU_SCU_I2C0
CK_SCU_SCU_I2C1
CK_SCU_SCU_SEQ
The clocks are controlled using the following registers.
Controlled Block Name
from:
CPU TOPREG
HOSTIFC HOS_SEQ_REG
SCU SCU_SEQ_REG
Table SCU (Sensor Control Unit)-84 Control of each Clock
Control from the Control
Upper CPU Sequencer of SCU
possible possible
－
possible
possible possible
possible possible
possible possible
possible possible
Table SCU (Sensor Control Unit)-85 Clock Control Registers
Register Name
SCU_CKEN
HOS_SCU_POWER
SCU_ISOP_POWER
from Internal
offset Remarks
0x071c TOPREG Control Region
0x0010 HOSTIFC Register Internal Sequencer Control
Region
0x0044 SCU Register Internal Sequencer Control Region
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CXD5602 User Manual
Control from Internal Sequencer of
HOSTIFC
possible
－
－
－
－
－