Sony CXD5602 User Manual page 231

3.8.8 IDMAC
The functions of the IDMAC have been modified based on the PrimeCell
Limited.
Features of the IDMAC

There are five DMA channels, each of which supports unidirectional transfer.

Accepts transfer requests from IMG_SSP and IMG_UART

Enables single data transfer and burst data transfer. In the case of burst data transfer, the size can be set by
the program

Enables Scatter/Gather transfer by use of the linked list.

Each channel has an independent 16 byte FIFO built in.

Supports only little endian
DMACSREQ[15:0]
DMACBREQ[15:0]
DMACLSREQ[15:0]
DMACLBREQ[15:0]
DMACCLR[15:0]
DMACTC[15:0]
DMACINTR
HADDR[11:2]
HWDATA[31:0]
HWRITE
HSEL
HTRANS[1:0]
HSIZE[2:0]
HBURST[2:0]
HREADYIN
HRDATA[31:0]
HRESP[1:0]
HREADYOUT
Channel0
Request
Channel1
And
Response
Channel2
Channel3
Interrupt
Request
Channel4
Channel5
AHB
Slave
Channel6
Interface
Channel7
Unimplemented
Figure DMAC-49 IDMAC Function Block Diagram
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CXD5602 User Manual
®
DMA Controller (PL080) from ARM
AHB Master 1
Bus
Internal
Interface
Arbiter
Bus
Request
AHB Master 2
Bus
Internal
Interface
Arbiter
Bus
Request
HADDRM1[31:0]
HWRITEM1
HSIZEM1[2:0]
HPROTM1[3:0]
HLOCKM1
HTRANSM1[1:0]
HBURSTM1[2:0]
HWDATAM1[31:0]
HRDATAM1[31:0]
HRESPM1[1:0]
HREADYINM1
HBUSREQM1
HGRANTM1
HADDRM2[31:0]
HWRITEM2
HSIZEM2[2:0]
HPROTM2[3:0]
HLOCKM2
HTRANSM2[1:0]
HBURSTM2[2:0]
HWDATAM2[31:0]
HRDATAM2[31:0]
HRESPM2[1:0]
HREADYINM2
HBUSREQM2
HGRANTM2