Sony CXD5602 User Manual page 936

RCOSC
XOSC
SYSPLL
1/2
1/3
1/4
1/5
CKSEL_ROOT.CPU_PLL_DIV5
CKSEL_ROOT.RFPLL1_STAT_CLK_SEL4
RTC_CLK_IN
(32.768kHz)
RF_CLK_IN
(Refer to GNSS)
CKSEL_ROOT.SEL_RF_PLL_0
SPI2_SCK
AP_CLK_IN
Figure SYSIOP Clock and Reset Control-116 SYSIOP Clock Configuration Diagram
3.14.3.2 Overview of SYSIOP Maximum Frequency
The following tables describe the maximum operating frequencies of the System and I/O Processor and the
SYSTEM Bus – the main function blocks of the SYSIOP. Each has a different maximum operating frequency
depending on the supported XOSC frequency and the SYSPLL oscillating frequency. The SYS SRAM within the
SYSIOP has the same operating frequency as the System and I/O Processor. The element circuits (BackUp SRAM,
DMAC, Crypto...) directly connected to the SYSTEM Bus or via a synchronous bridge basically have the same
maximum frequencies as the SYSTEM Bus.
For the maximum operating frequencies of external communication interfaces, refer to each respective Part. For
the XOSC and SYSPLL frequency settings, refer to Section 3.5.
Table SYSIOP Clock and Reset Control-760 XOSC (26 MHz), High Performance Mode
Clock source
frequency
System and I/O Processor
System Bus
0
1
ck_rf_pll_1
2
3
0
1
0
1
ck_cpu_bus
2
3
DIV(0)
CKSEL_ROOT.STAT_CLK_SEL4L
0
1
DIV(4)
0
1/2 1
ck_scu_xtal
1/3 2
1/4 3
CKSEL_SCU.SEL_SCU_XTAL
0
1/250
1 ck_host
2
3
DIV(5)
SEL(0)
0
1
ck_freqdis_pre
2
3
Reserved
0
1/2 1
2
1/4
3
SEL(5) SEL(4)
M Hz
M Hz
M Hz
ck_cpu_bus_gear_1
1/M
ck_ahb_gear
1/M
DIV(1)
ck_co m_gear
1/M
CK
CG(SUB1) GATE
ck_sf c_sf clk_gear
1/M
1/2
DIV(3)
0
1
ck_scu_pre
2
1/250
0 ck_32k_pre
Reserved 3
1
CKSEL_SCU.SEL_SCU
CKSEL_SCU.SEL_SCU_32K
ck_ho st_gear
1/M
0 ck_ho st2
CK
1
CG(SYS02) GATE
SEL(1)
0
1
2
3
Reserved
SEL(3)
0
1
SEL(2)
ck_apb_gear
1/M
DIV(2)
0
1/250
1
ck_rtc_pre
2
3
Reserved
CKSEL_ROOT.PMU_STAT_CLK_SEL4
SYSPLL XOSC
195.000 156.000
97.500 78.000
48.750 39.000
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CXD5602 User Manual
System and
I/O Processor
DCLK
HCLK
SCLK
FCLK
SYSTEM Bus
HCLK
SPI0
CK
SSPCLK
CG(SUB04) GATE
PCLK
UART1
CK
UARTCLK
CG(SUB03) GATE
CK
PCLK
CG(SUB10) GATE
I2C2
CK
I2CCLK
CG(SUB05) GATE
PCLK
AHB/APB
BusBridge
CK_AHB_BRG_COMIF
CK
CG(SUB00) GATE
SDMAC
CK
HCLK
CG(SYS05) GATE
HDMAC
CK
HCLK
CG(SYS06) GATE
SYDMAC
CK
HCLK
CG(SYS07) GATE
SYSUBDMAC
CK
HCLK
CG(SUB02) GATE
SPI Flash Controller
CK
HCLK
CG(SUB07) GATE
CK
SFCLK
GATE
CG(SUB08)
ck_sf c_hclk_lo w_gear
CK
SFC_HCLK
GATE
CG(SUB09)
AHB/AHB
BusBridge
CK_BRG_SCU
CK
CG(SYS14) GATE
Crypto
CK
HCLK
CG(SUB06) GATE
SPI2
SSPCLK
CK
PCLK
CG(SYS17) GATE
I2C3
CK
I2CCLK
GATE
CG(SYS03)
CK
PCLK
GATE
CG(SYS16)
UART0
CK
UARTCLK
CG(SYS00) GATE
CK
PCLK
CG(SYS01) GATE
SEQ
CK
SEQ_CLK
CG(SYS15) GATE
PCLK
PCLK_CG
AHB/APB
BusBridge
CK CK_BRG_HOST
CG(SYS04) GATE
FreqDisc
CK_APB
CK
PCLK
CG(SYS08) GATE
CK
CK_REF
GATE
CG(SYS09)
CK
ISI G[0]
GATE
CG(SYS10)
ISI G[1]
CK
ISI G[2]
GATE
CG(SYS11)
CK
ISI G[6]
CG(SYS12) GATE
RTC0
Register
PCLK
CK
CK_RTC
CG(SYS13) GATE
CK_RTC
CK_RTC_INV
RTC1
Register
PCLK
CK_RTC
CK_RTC
CK_RTC_INV
AHB/APB
BusBridge
RCOSC RTC
26.000 8.192 0.032768
26.000 8.192 0.032768
26.000 8.192 0.032768