Sony CXD5602 User Manual page 220

3.8 DMAC
3.8.1 Overview and Features
List of DMACs

SDMAC (Power domain: PWD_SYSIOP)
The SDMAC is for the Sensor and performs DMA transfer between the SCU and each SRAM

HDMAC (Power domain: PWD_SYSIOP)
The HDMAC is for the HOSTIFC and performs DMA transfer between the HOSTIFC and each SRAM

SYDMAC (Power domain: PWD_SYSIOP)
The SYDMAC is for the System and performs DMA transfer between each SRAM

SYSUBDMAC (Power domain: PWD_SYSIOP_SUB)
The SYSUBDMAC is for the System and performs DMA transfer of each SRAM, and data store and
load to/from the FLASH

ADMAC (Power domain: PWD_APP_DSP)
The ADMAC is for the Application processor and performs DMA transfer between each SRAM

IDMAC (Power domain: PWD_APP_SUB)
The IDMAC performs DMA transfer of the Display and Wi-Fi data
3.8.2 Function Descriptions

SDMAC
®
The PrimeCell µDMA Controller (PL230) from ARM Limited is equipped. There are 32 channels of DMA
channels. For details, refer to the PrimeCell
This Controller adds a feature to notify the CPU of independent interrrupts of each DMA channel.

HDMAC, SYDMAC, SYSUBDMAC, ADMAC
®
The PrimeCell Single Master DMA Controller (PL081)
®
the PrimeCell Single Master DMA Controller (PL081)
This Controller adds a feature to notify the CPU of independent interrrupts of each DMA channel.

IDMAC
The functions have been modified based on the PrimeCell
®
µDMA Controller (PL230) Technical Reference Manual.
from ARM Limited is equipped. For details, refer to
Technical Reference Manual.
®
DMA Controller (PL080) from ARM Limited.
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CXD5602 User Manual