Sony CXD5602 User Manual page 957

Table ADC-771 Sampling Rate Range Supported by the HPADC
Clock Source Clock Frequency (Input to
SCU)
RCOSC 8.192 MHz
1 Hz to 32.768 kHz
RTC 1 Hz to 32.768 kHz
XOSC 13 MHz
3.21.2 ADC Block Diagram
Figure 3.26-1 describes the block diagram of the ADCIF module and around ADC macro circuits.
SCU
SCU_ANALOG
SEN_AIN2
1
LPADC_Wrapper
SEN_AIN3
1 LPAD_HV_AIN0
SEN_AIN4 LPAD_HV_AIN1
1
LPAD_HV_AIN2
SEN_AIN5 LPAD_HV_AIN3
1
LPAD_LV_CHSEL
toggle data
( 0 <-> 1 )
toggle data
( 0, 1, 2, 3 )
HPADC_Wrapper
SEN_AIN0
1
HPAD_HV_AIN0
SEN_AIN1
1
HPAD_HV_AIN1
Figure ADC-118 Block Diagram ADCIF module and around ADC macro circuits
3.21.3 Memory Map
Figure ADC-119 describes a memory map inside the ADCIF.
For the memory map seen from the higher layers, refer to Chapter of the SCU (3.9).
Supported Sampling Rate Range
16 kHz to 32 kHz
1 Hz to 32.768 kHz
1 Hz to 32.768 kHz
16.927 kHz to 33.854 kHz
for GNSS
R
LPAD_LV_CHSEL_OUT
R
LPAD_LV_DOUT
HPAD_LV_DATA_EN0
HPAD_LV_DOUT0
HPAD_LV_DATA_EN1
HPAD_LV_DOUT1
SCU_PWM
LPADC_EN OAD_EN
HPADC_EN
－957/1010－
Over Sampling Frequency
2.048 MHz
None (actual rate conversion)
None (actual rate conversion)
2.167 MHz
SCU_ANALOG
decimation SCU_ADCIF_FIFO (L0)
16 words
decimation SCU_ADCIF_FIFO (L1)
16 words
SCU_ADCIF_FIFO (L2)
decimation
16 words
decimation SCU_ADCIF_FIFO (L3)
16 words
2's Comp.
CIC3 SCU_ADCIF_FIFO (H0)
Filter 32 words
2's Comp.
CIC3 SCU_ADCIF_FIFO (H1)
Filter 32 words
2's Comp.
CXD5602 User Manual
SCU_ADCIF_
FIFOIF
SCU_ADCIF_MUX
APB
APB
FIFO control
SCU_ADCIF_REG
APB
decimation control
LPADC control
HPADC control
interrupt
DMA_REQ / ACQ