System Memory; Backup Memory; Clock And Reset; Overview - Sony CXD5602 User Manual

2.6.3

System Memory

There is 256 KByte SRAM in total which is connected to the AHB of the System and I/O Processor.
The SRAM block is made up of four 64K Byte Logic Tiles. One tile of the four is divided into four sub Logic
Tiles of: 8 KByte, 8 KByte, 16 KByte, and 32 KByte.
Each Logic Tile has the AHB I/F individually. The application program can access data from each Logic Tile via
local AHB. In addition, the Logic Tile is the unit for the SRAM access protection function. You can use
protection feature that keeps masters with specific Master ID from accessing specific SRAM Logic Tiles. The
protection feature can be controlled via buses. You can assign only Arm
that can control the protection feature. Shortly after the POR, all masters can access all Logic Tiles.
Power domain is PWD_CORE. When PWD_CORE is turned OFF, this memory cannot be used. Each sub area
tile is allocated to serial addresses; therefore, each sub Logic Tile can be turned ON/OFF individually. There are
two operation modes for the SRAM power-off: Retention mode and Shutdown mode. They can be set by system
control registers.
2.6.4

Backup Memory

There is 64 KByte SRAM in total which is connected to the AHB in System and IOP Domain for backup.
You can use protection feature that keeps masters with specific Master ID from accessing specific SRAM Logic
Tiles. The protection feature can be controlled via buses.
Power domain belongs to PWD_PMU area. You can use protection feature that keeps masters with specific
Master ID from accessing specific SRAM Logic Tiles. The protection feature can be controlled via buses. Power
ON/OFF can be controlled by registers. There are two operation modes for the SRAM power-off: Retention mode
and Shutdown mode. They can be set by system control registers.
2.7

Clock and Reset

2.7.1

Overview

The clock architecture inside the CXD5602 enables circuit blocks to select a variety of clock sources. It can
support wide range of application with optimized power consumption, from low speed sensing operation with low
power consumption, to high speed application processing using multi-core processor.
The CXD5602 has five types of usable clock sources and is made up of main five clock domains in accordance
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CXD5602 User Manual
Cortex ® -M0+ of SYSCPU as master