Sony CXD5602 User Manual page 818

Caution: The frequencies supported for internal oscillation mode is 26 MHz.
The frequencies supported for external clock mode is 26 MHz.
Note 2: The settings differ for each crystal oscillator frequency. The IXO_LV_I_VAL1 (before oscillation starts)
and IXO_LV_I_VAL3 (after changing the current setting) parameter values are tentative values. During external
clock mode, set to "8'd0".
Event
PWD_SCU Reset
Release
LPADC Reset Release
HPADC Reset Release
For clock control refer to the PMU (3.4) Chapter.
Event Control
Register
Location
LPADC SCU.ADC
Operation IF
Enable
HPADC0 SCU.ADC
Operation IF
Enable
HPADC1 SCU.ADC
Operation IF
Enable
Reset SCU.ADC
Table SCU (Sensor Control Unit)-701 Main Reset Control
Control Address bit
Register
Location
TOPREG 0x0060 [16]
[0]
TOPREG 0x0704 [4]
TOPREG 0x0704 [2]
Table SCU (Sensor Control Unit)-702 Sub Reset Control
Address bit Name
0x0018de00 [0] LV_ADC_EN
0x0018de10 [0] SW_RESET
0x0018de84 [0] LV_ADC0_EN
[1] LV_ADC0_REF_EN
[2] LV_LPF0_EN
0x0018de88 [0] LV_CLKOUT0_EN
0x0018de90 [0] SW_RESET
0x0018dec4 [0] LV_ADC0_EN
[1] LV_ADC0_REF_EN
[2] LV_LPF0_EN
0x0018dec8 [0] LV_CLKOUT0_EN
0x0018ded0 [0] SW_RESET
0x0018de10 [0] SW_RESET
Name
WEN_PWD_SCU
PWD_SCU
XRST_SCU_LPADC
XRST_SCU_HPADC
Setting
Value
1'b1
1'b1
1'b1
1'b1
1'b1
1'b1
1'b1
1'b1
1'b1
1'b1
1'b1
1'b1
==0
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CXD5602 User Manual
Setting Descriptions
Value
1'b1 PWD_SCU reset
Write Enable
1'b1 PWD_SCU reset release
1'b1 LPADC reset release
1'b1 LPADC reset release
Descriptions
LPADC operation enable
FIFO reset
HPADC0 operation
permission /stop
LPF0 Enable control terminal.
ADC0 REF circuit enable
ADC0 clock output enable
FIFO reset
HPADC1 operation
permission/stop
LPF1 enable control terminal
ADC1 REF circuit enable
ADC1 clock output enable
FIFO reset
Confirms whether turns to "0"
control