Sony CXD5602 User Manual page 876

3.10.2.2 Register Descriptions
Table SPI-749 shows descriptions of the registers added for control of Chip Select.
Register
Address
Name
0x041AB090 CS_MODE
0x041AB094 SSP_CS
3.10.2.3 Clock and Reset
Figure SPI-96 shows the clock and reset system diagram of the SPI0.
To access the SPI0 register, supply the clock to the AHB/APB Bus Bridge.
RTC_CLK_IN
(32.768kHz)
SYSPLL
1/2
1/3
1/4
1/5
CKSEL_ROOT.CPU_PLL_DIV5
CKSEL_ROOT.RFPLL1_STAT_CLK_SEL4
CKSEL_ROOT.STAT_CLK_SEL4
SYSIOP_SUB_CKEN.SPIM
SYSIOP_SUB_CKEN.COM_BRG
CKDIV_CPU_DSP_BUS.CK_M0
CKDIV_CPU_DSP_BUS.CK_AHB
SYSIOP_SUB_CKEN.AHB_BRG_COMIF
Table SPI-733 SPI0 register Descriptions
Bit Field
Type
Name
Reserved RO
cs_mode RW
Reserved RO
ssp_cs RW
RCOSC
0
ck_rf_pll_1
1 ck_cpu_bus
2
XOSC
3 1/M
0
1
2
3
0
1
CKDIV_COM.CK_COM
1/M
Figure SPI-96 SPI0 Clock and Reset System
－876/1010－
Initial
Bit Description
Value
[15:1] 0 Reserved
[0] 1'b0 Chip Select (CS)
0: Uses CS of PL022
1: Uses CS of SSP_CS (register setting)
[15:1] 0 Reserved
[0] 1'b1 Chip Select setting
0: SPI communication active
1: SPI communication inactive
ck_co m_gear
ck_ahb_gear
1/M
Auto(PWD_SYSIOP_SUB Power Domain ON)
PWD_RESET0.PWD_SYSIOP_SUB
SWRESET_BUS.XRST_SPIM
CXD5602 User Manual
SPI0
CK
SSPCLK
GATE
PCLK
nSSPRST
PRESETn
AHB/APB
CK
GATE
BusBridge
CK
GATE