Sony CXD5602 User Manual page 956

3.21 ADC
3.21.1 ADC Overview
Analog input function comprises the SCU_ADCIF module including a logic to control LPADC (4ch) and HPADC
(2ch), and the SCU_ANALOG module including the ADC analog circuits and the peripheral circuits.
The ADCIF module distributes 10 bit A/D conversion data from the LPADC to four time-sharing lines and stores
them in the FIFO. In the meantime, the ADCIF module applies a decimation filter comprising the third order CIC
filter to two 10 bit A/D conversion data, which are from the individual two HPADCs separately. These data are
stored in the FIFO as 16 bit data. Regarding conversion data from the HPADC, two data-writing modes can be
selected. One is a mode called vector mode (dual axis) that packs two A/D conversion data, and then writes them
in the FIFO. The other is a mode that writes two A/D conversion data in the FIFO separately. These FIFOs which
are used only for the ADC in the ADCIF module are referred to as SCU_ADCIF_FIFOs in this manual. Four
channels of 16 rows of SCU_ADCIF_FIFOs are prepared for the LPADC, and two channels of 32 rows are
prepared for the HPADC. Each channel has an interface for DMA REQ/ACK signals to perform DMA processing,
and for interrupt signals to perform Watermark Level detection.
Furthermore, the ADCIF module has a register block to control analog circuits, and the APB interface to exchange
data with the CPU and the SCU internal sequencer.
For data storage at the SCU and the FIFO control inside the SCU, refer to Chapter of the SCU (3.9).
The ADCIF module has two ports for GNSS, one is 10 bit A/D conversion data, and the other is the enable signal,
to directly output the values of a selected channel in the LPADC.
3.21.1.1 LPADC (Low Power ADC) Sampling Frequency
Table ADC-810 describes sampling frequencies supported by the LPADC. The maximum sampling rate is
dependent on the number of active channels.
Clock Source of
CK_U32KL
RCOSC
RTC
3.21.1.2 HPADC (High Performance ADC) Sampling Frequency
Table ADC-811 describes sampling frequencies supported by the HPADC
Table ADC-770 Sampling Rate Range Supported by the LPADC
Clock Frequency Supported Sampling Rate Range vs number of active channels
(Input to SCU)
1 channel
8.192 MHz 1 Hz to 32 kHz
32.768 kHz 1 Hz to 32 kHz
2 channels
1 Hz to 512 Hz
1 Hz to 512 Hz
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4 channels
1 Hz to 256 Hz
1 Hz to 256 Hz