Sony CXD5602 User Manual page 225

3.8.3.4 Clock Supply Start and Stop
3.8.3.4.1 Clock Supply Start
Perform the following control to start supplying the HCLK clock of the SDMAC.
1. Reset release
Automatically released when the PWD_SYSIOP power domain is turned ON.
2. Clock supply start
SYSIOP_CKEN.AHB_DMAC0=1'b1
3.8.3.4.2 Clock Supply Stop
Perform the following control to stop supplying the HCLK clock of the SDMAC.
1. Clock supply stop
SYSIOP_CKEN.AHB_DMAC0=1'b0
3.8.4 HDMAC
Adds a feature to notify the CPU of independent interrupts of each DMA channel to the
DMA Controller (PL081). Figure DMAC-44 shows an overview of the added functions.
HDMAC(PL081)
Conventional logic
Chennel0
IntErrCh0
IntTCCh0
Chennel1
IntErrCh1
IntTCCh1
Figure DMAC-44 HDMAC Overview of Added Functions
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INTERR
INTTC
INTR
Additional logic
DMACINTR0
DMACINTR1
CXD5602 User Manual
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